wiki:Component/VciMultiRam

Version 1 (modified by alain, 17 years ago) (diff)

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SocLib Components General Index

VciMultiRam Functional Description

This VCI target is an embedded SRAM controller. This hardware component implements up to 16 independent memory segments : Each segment is defined by a BASE address and a SIZE (number of bytes). Both the BASE and the SIZE parameters must be multiple of 4. The segments allocated to a given instance of this component is defined in the mapping table.

Each segment is implemented as aa array of int dynamically allocated in the constructor. A segment can be initialised using the

VciMultiRam CABA Implementation

The caba implementation is in

Template parameters:

  • The VCI parameters

Constructor parameters

VciMultiRam(
     sc_module_name name,   // Instance name
     const soclib::common::IntTab &index,   //  Target index
     const soclib::common::MappingTable &mt,   // Mapping Table
     soclib::common::ElfLoader &loader);

Ports

  • sc_in<bool> p_resetn : Global system reset
  • sc_in<bool> p_clk : Global system clock
  • soclib::common::VciiTarget<vci_param> p_vci : The VCI port