Changes between Version 1 and Version 2 of Component/Vci Multi Timer

Timestamp:

May 5, 2007, 2:19:23 PM (18 years ago)

Author:

alain

Comment:

--

Component/Vci Multi Timer

@@ -6 +6 @@
 The memory segment allocated to this component must be aligned
 on 4K bytes boundary.
-The timer index i is defined by the ADDRESS[12:4] bits.
+The timer index i is defined by the ADDRESS![12:4] bits.
 This hardware component cheks for segmentation violation, and can be used
 as a default target.
@@ -12 +12 @@
 Each timer contains 4 memory mapped registers:
 
- * '''TIMER_VALUE'''     : ADDRESS[3:0] = 0x0
+ * '''TIMER_VALUE'''     : ADDRESS![3:0] = 0x0
 This 32 bits register is unconditionnally incremented at each cycle.
 A read request returns the current time contained in this register.
 A write request sets a new value in this register.
 
- * '''TIMER_RUNNING''' : ADDRESS[3:0] = 0x4 
+ * '''TIMER_RUNNING''' : ADDRESS![3:0] = 0x4 
 When the Boolean value contained in this register is true, 
 the corresponding interrupt is enabled.  
@@ -23 +23 @@
 A write request of a non-zero value sets this registe.
 
- * '''TIMER_PERIOD'''    : ADDRESS[3:0] = 0x8
+ * '''TIMER_PERIOD'''    : ADDRESS![3:0] = 0x8
 This 32 bits register defines the period between two successive interrupts.
 A write request writes a new value in this register, and the TIMER_RUNNING
@@ -29 +29 @@
 A read request returns the current value in this register.
 
- * '''TIMER_RESETIRQ''' : ADDRESS[3:0] = 0xC
+ * '''TIMER_RESETIRQ''' : ADDRESS![3:0] = 0xC
 Any write request in this Boolean register will reset the pending IRQ.
 A read request returns the zero value when there is no pending interrupt,