Changes between Version 7 and Version 8 of Component/Vci Mwmr Controller

Timestamp:

Feb 25, 2008, 2:36:00 PM (17 years ago)

Author:

Nicolas Pouillon

Comment:

Update doc

Component/Vci Mwmr Controller

@@ -28 +28 @@
 
 As a target this component contains the following memory mapped registers:
- * Registers 0 to `MWMR_IOREG_MAX`
+ * Registers 0 to `MWMR_IOREG_MAX-1`
 When read from, they reflects status registers, when written to, they reflects the control registers.
 
@@ -38 +38 @@
 NO may be any MWMR channel in the selected way.
 
- * `MWMR_CONFIG_STATE_ADDR`
-Sets the address of state field for the selected MWMR channel.
-
- * `MWMR_CONFIG_OFFSET_ADDR`
-Sets the address of read/write pointer field for the selected MWMR channel.
-
- * `MWMR_CONFIG_LOCK_ADDR`
-Sets the address of the lock protecting the selected MWMR channel.
+ * `MWMR_CONFIG_STATUS_ADDR`
+Sets the address of the status descriptor structure for the selected MWMR channel.
 
  * `MWMR_CONFIG_DEPTH`
-Sets the depth of the selected MWMR channel.
+Sets the total depth of the selected MWMR channel (in bytes).
 
- * `MWMR_CONFIG_WIDTH`
-Sets the width of the selected MWMR channel. This will determine the atomic transfer block size. This must be multiple of 4 bytes.
-
- * `MWMR_CONFIG_BASE_ADDR`
+ * `MWMR_CONFIG_BUFFER_ADDR`
 Sets the address of the data buffer for the selected MWMR channel.
 
@@ -88 +79 @@
 VciMwmrController(
         sc_module_name name,  // instance name
-        const IntTab &index,  // VCI target index
         const MappingTable &mt,  // mapping table
+        const IntTab &srcid,  // VCI initiator index
+        const IntTab &tgtid,  // VCI target index
         const size_t plaps,    // time between two access to a given channel
-        const size_t fifo_depth,   // hardware FIFOs depth
+        const size_t fifo_to_coproc_depth,   // hardware FIFOs depth
+        const size_t fifo_from_coproc_depth,   // hardware FIFOs depth
         const size_t n_to_coproc,  // number of read MWMR channels
         const size_t n_from_coproc, // number of write MWMR channels