Changes between Version 9 and Version 10 of Component/Vci Mwmr Dma

Timestamp:

Apr 9, 2015, 4:45:43 PM (9 years ago)

Author:

alain

Comment:

--

Component/Vci Mwmr Dma

@@ -8 +8 @@
 
 On the coprocessor side, it provides a variable number of TO_COPROC and FROM_COPROC ports,  defining a fifo-like interface, without addresses. 
- * on a TO_COPROC port the coprocessor can request to read a vector of 32 bits words.
- * on a FROM_COPROC port the coprocessor can request to write a vector of 32 bits words.  
+ * on a TO_COPROC port the coprocessor can request to read a burst of 32 bits words.
+ * on a FROM_COPROC port the coprocessor can request to write a burst of 32 bits words.  
 Each TO_COPROC or FROM_COPROC port define a communication channel to a memory buffer. 
 The number of TO_COPROC and FROM_COPROC channels, are constructor parameters. 
@@ -19 +19 @@
 It makes the assumption that the VCI RDATA & WDATA fields have 32 bits, but the VCI address field can have up to 64 bits. The VCI TRDID and PKTID fields must have at least 4 bits.
 
-'''WARNING''' : This DMA controller uses bursts to transfer the data, and a constructor parameter define the burst size (typically a cache line). This introduce the following constraints:
- * The memory buffer address and size  must be multiple of the burst size.
- * The number of bytes requested by the coprocessor on a TO_COPROC or FROM_COPROC port must be an integer number of bursts.
+'''WARNING''' : This DMA controller uses bursts to transfer the data. The burst size is a constructor parameter (typically a cache line). This introduce the following constraints:
+ * The memory buffer address and size must be multiple of the burst size.
+ * The number of bytes requested by the coprocessor on a TO_COPROC or FROM_COPROC port is an integer number of bursts.
 
-Each channel FSM implements two main operating modes that can be defined by software:
- * In '''MODE_DMA_IRQ''' or '''MODE_DMA_NO_IRQ''', the channel FSM transfer a single buffer between the memory and the coprocessor port. The number of VCI burst depends on both the memory buffer size, and the burst size. In this mode the software must define the channel configuration by writing the data buffer address and size in the channel configuration registers, and starts the transfer by writing a non zero value in the CHANNEL_RUN register. When the transfer is completed, the channel FSM is blocked, waiting in the CHANNEL_SUCCESS or CHANNEL_ERROR state, until it is reset to IDLE state by writing a zero value in the CHANNEL_RUN register. In MODE_DMA_IRQ an IRQ is activated when the requested transfer is completed. 
+Each channel FSM implements two main operating modes that can be defined by software using configuration registers.
+ * In '''MODE_DMA_IRQ''' or '''MODE_DMA_NO_IRQ''', the channel FSM transfer a single buffer between the memory and the coprocessor port. The number of VCI burst depends on both the memory buffer size, and the burst size. In this mode the software must define in configuration registers the mode, the data buffer physical address, and the buffer size. It starts the transfer by writing a non zero value in the CHANNEL_RUNNING register. When the transfer is completed, the channel FSM is blocked, waiting in the CHANNEL_SUCCESS or CHANNEL_ERROR state, until it is reset to IDLE state by writing a zero value in the CHANNEL_RUNNING register. In MODE_DMA_IRQ an IRQ is activated when the requested transfer is completed. 
 
- * In '''MODE_MWMR''', the channel FSM transfer an "infinite" data stream, between the coprocessor port and a MWMR channel (software FIFO in memory). In this mode the software must write in the channel configuration registers the data buffer address and size, but also the MWMR FIFO descriptor address and the lock address. It starts the transfer by writing a non zero value in the CHANNEL_RUN register. The channel FSM implements an infinite loop to execute the 7 steps MWMR protocol: 
+ * In '''MODE_MWMR''', the channel FSM transfer an "infinite" data stream, between the coprocessor port and a MWMR channel (software FIFO in memory). In this mode the software must define the mode, the data buffer physical address, and the buffer size, but also the MWMR FIFO descriptor address and the lock address in configuration registers. It starts the transfer by writing a non zero value in the CHANNEL_RUNNING register. The channel FSM implements an infinite loop to execute the 7 steps MWMR protocol: 
    1 - Read the ticket for queuing lock (1 flit VCI READ)
    2 - Increment atomically the ticket (VCI CAS)
@@ -34 +34 @@
    6 - Upate the status (3 flits VCI WRITE)
    7 - Release the lock (1 flit VCI WRITE)
-The IRQ is not used in normal operation. AN IRQ is asserted if a VCI error is reported, ant the channel FSM is blocked, waiting in CHANNEL_ERROR state until it is reset to IDLE state by writing a zero value in the CHANNEL_RUN register. 
+The IRQ is not used in normal operation. AN IRQ is asserted if a VCI error is reported, ant the channel FSM is blocked, waiting in CHANNEL_ERROR state until it is reset to IDLE state by writing a zero value in the CHANNEL_RUNNING register. 
 
 The various VCI transactions corresponding to different channels are interleaved and parallelized on the VCI network. The maximum number of simultaneous VCI transactions is equal to the number of channels. 
@@ -55 +55 @@
  * '''CHANNEL_MODE[k]'''           MWMR / DMA_IRQ / DMA_NO_IRQ                 (MWMR or DMA)
  * '''CHANNEL_SIZE[k]'''           data buffer size (bytes)                    (MWMR or DMA) 
- * '''CHANNEL_RUN[k]'''            channel activation/deativation              (MWMR or DMA)
+ * '''CHANNEL_RUNNING[k]'''        channel activation/deativation              (MWMR or DMA)
  * '''CHANNEL_STATUS[k]'''         channel FSM state                           (MWMR or DMA)