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Changes between Version 12 and Version 13 of Component/Vci Mwmr Dma

-                      v12
+                      v13
  * In '''MODE_MWMR''', the channel FSM transfer an "infinite" data stream, between the coprocessor port and a MWMR channel (software FIFO in memory). In this mode the software must define the mode, the data buffer physical address, and the buffer size, but also the MWMR FIFO descriptor address and the lock address in configuration registers. It starts the transfer by writing a non zero value in the CHANNEL_RUNNING register. The channel FSM implements an infinite loop to execute the 7 steps MWMR protocol:
  * Read the ticket for queuing lock (1 flit VCI READ)
  * Increment atomically the ticket (VCI CAS)
  * Read the lock current value (1 flit VCI READ)
  * Read the channel status (3 flits VCI READ)
  * Transfer the data (N flits VCI READ or WRITE)
  * Upate the status (3 flits VCI WRITE)
  * Release the lock (1 flit VCI WRITE)
+  * Read the ticket for queuing lock (1 flit VCI READ)
+  * Increment atomically the ticket (VCI CAS)
+  * Read the lock current value (1 flit VCI READ)
+  * Read the channel status (3 flits VCI READ)
+  * Transfer the data (N flits VCI READ or WRITE)
+  * Upate the status (3 flits VCI WRITE)
+  * Release the lock (1 flit VCI WRITE)
 The IRQ is not used in normal operation. AN IRQ is asserted if a VCI error is reported, ant the channel FSM is blocked, waiting in CHANNEL_ERROR state until it is reset to IDLE state by writing a zero value in the CHANNEL_RUNNING register.