Changes between Version 5 and Version 6 of Component/Vci Mwmr Dma


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Timestamp:
Apr 9, 2015, 1:47:46 PM (9 years ago)
Author:
alain
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  • Component/Vci Mwmr Dma

    v5 v6  
    2323 * The number of bytes requested by the coprocessor on a TO_COPROC or FROM_COPROC port must be an integer number of bursts.
    2424
    25 Each channel FSM implements two operating modes that can be defined by software:
    26  * In '''DMA_MODE''', the channel FSM transfer a single buffer between the memory and the coprocessor port. The number of VCI burst depends on both the memory buffer size, and the burst size. In this mode the software must define the channel configuration by writing the data buffer address and size in the channel configuration registers. An optional interrupt can be activated when the requested transfer is completed.
     25Each channel FSM implements two main operating modes that can be defined by software:
     26 * In '''MODE_DMA_IRQ''' or '''MODE_DMA_NO_IRQ''' modes the channel FSM transfer a single buffer between the memory and the coprocessor port. The number of VCI burst depends on both the memory buffer size, and the burst size. In this mode the software must define the channel configuration by writing the data buffer address and size in the channel configuration registers. When the transfer is completed, the channel FSM wait in the success or ERROR state, until it is reset to IDLE state by writing a zero value in the CHANNEL_RUN register. An optional IRQ can be activated when the requested transfer is completed (only in MODE_DMA_IRQ).
     27
    2728 * In '''MWMR_MODE''', the channel FSM transfer an "infinite" data stream, between the coprocessor port and a MWMR channel (software FIFO in memory). In this mode the software must write in the channel configuration registers the data buffer address and size, but also the MWMR FIFO descriptor address and the lock address, as the channel FSM implements the 7 steps MWMR protocol.
    2829   1 - Read the ticket for queuing lock (1 flit VCI READ)
    … …  
    3233   5 - Transfer the data (N flits VCI READ or WRITE)
    3334   6 - Upate the status (3 flits VCI WRITE)
    34    7 - Release the lock (1 flit VCI WRITE)
     35   7 - Release the lock (1 flit VCI WRITE)
     36For an "infinite" data stream, the IRQ is not used in normal operation, and is only asserted if a VCI error is reported, ant the channel FSM is waiting in one ERROR state.
    3537
    3638Several channels can simultaneously run in different modes, and the various VCI transactions corresponding to different channels are interleaved and parallelized on the VCI network. The maximum number of simultaneous VCI transactions is equal to the number of channels.
    … …  
    4547For each communication channel, the software addressable registers are the following
    4648 * '''CHANNEL_BUFFER_LSB[k]'''     data buffer physical address 32 LSB bits    (MWMR or DMA)
     49 * '''CHANNEL_BUFFER_MSB[k]'''     data buffer physical address extend bits    (MWMR or DMA)
     50 * '''CHANNEL_MWMR_LSB[k]'''       channel status physical address 32 LSB bits (MWMR   only)
     51 * '''CHANNEL_MWMR_MSB[k]'''       channel status physical address extend bits (MWMR   only)
     52 * '''CHANNEL_LOCK_LSB[k]'''       channel lock physical address 32 LSB bits   (MWMR   only)
     53 * '''CHANNEL_LOCK_MSB[k]'''       channel lock physical address extend bits   (MWMR   only)
     54 * '''CHANNEL_WAY[k]'''            channel direction (TO_COPROC / FROM_COPROC) (MWMR or DMA)
     55 * '''CHANNEL_MODE[k]'''           MWMR / DMA_IRQ / DMA_NO_IRQ                 (MWMR or DMA)
     56 * '''CHANNEL_SIZE[k]'''           data buffer size (bytes)                    (MWMR or DMA)
     57 * '''CHANNEL_RUN[k]'''            channel activation/deativation              (MWMR or DMA)
     58 * '''CHANNEL_STATUS[k]'''         channel FSM state                           (MWMR or DMA)
    4759
    48  * '''CHANNEL_BUFFER_MSB[k]'''     data buffer physical address extend bits    (MWMR or DMA)
    49 
    50  * '''CHANNEL_MWMR_LSB[k]'''       channel status physical address 32 LSB bits (MWMR   only)
    51 
    52  * '''CHANNEL_MWMR_MSB[k]'''       channel status physical address extend bits (MWMR   only)
    53 
    54  * '''CHANNEL_LOCK_LSB[k]'''       channel lock physical address 32 LSB bits   (MWMR   only)
    55 
    56  * '''CHANNEL_LOCK_MSB[k]'''       channel lock physical address extend bits   (MWMR   only)
    57 
    58  * '''CHANNEL_WAY[k]'''            channel direction (TO_COPROC / FROM_COPROC) (MWMR or DMA)
    59 
    60  * '''CHANNEL_MODE[k]'''           MWMR / DMA_IRQ / DMA_NO_IRQ                 (MWMR or DMA)
    61 
    62  * '''CHANNEL_SIZE[k]'''           data buffer size (bytes)                    (MWMR or DMA)
    63 
    64  * '''CHANNEL_RUN[k]'''            channel activation/deativation              (MWMR or DMA)
    65 
    66  * '''CHANNEL_STATUS[k]'''                                                     (MWMR or DMA)
    67 
     60The relevant values for the CHANNEL_STATUS register are the following:
     61 *
    6862For extensibility issues, you should access these registers using these globally-defined offsets.
    6963The [source:trunk/soclib/soclib/module/infrastructure_component/dma_infrastructure/vci_mwmr_dma/include/soclib/mwmr_dma.h mwmr_dma.h file] defines all useful offsets and constants.
    … …  
    115109
    116110Not available yet.
    117