Changes between Version 6 and Version 7 of Component/Vci Mwmr Dma

Timestamp:

Apr 9, 2015, 3:33:49 PM (9 years ago)

Author:

alain

Comment:

--

Component/Vci Mwmr Dma

@@ -24 +24 @@
 
 Each channel FSM implements two main operating modes that can be defined by software:
- * In '''MODE_DMA_IRQ''' or '''MODE_DMA_NO_IRQ''' modes the channel FSM transfer a single buffer between the memory and the coprocessor port. The number of VCI burst depends on both the memory buffer size, and the burst size. In this mode the software must define the channel configuration by writing the data buffer address and size in the channel configuration registers. When the transfer is completed, the channel FSM wait in the success or ERROR state, until it is reset to IDLE state by writing a zero value in the CHANNEL_RUN register. An optional IRQ can be activated when the requested transfer is completed (only in MODE_DMA_IRQ). 
+ * In '''MODE_DMA_IRQ''' or '''MODE_DMA_NO_IRQ''' modes the channel FSM transfer a single buffer between the memory and the coprocessor port. The number of VCI burst depends on both the memory buffer size, and the burst size. In this mode the software must define the channel configuration by writing the data buffer address and size in the channel configuration registers. When the transfer is completed, the channel FSM is blocked, waiting in the SUCCESS or ERROR state, until it is reset to IDLE state by writing a zero value in the CHANNEL_RUN register. An optional IRQ can be activated when the requested transfer is completed (only in MODE_DMA_IRQ). 
 
  * In '''MWMR_MODE''', the channel FSM transfer an "infinite" data stream, between the coprocessor port and a MWMR channel (software FIFO in memory). In this mode the software must write in the channel configuration registers the data buffer address and size, but also the MWMR FIFO descriptor address and the lock address, as the channel FSM implements the 7 steps MWMR protocol.
@@ -59 +59 @@
 
 The relevant values for the CHANNEL_STATUS register are the following:
- *
-For extensibility issues, you should access these registers using these globally-defined offsets.
-The [source:trunk/soclib/soclib/module/infrastructure_component/dma_infrastructure/vci_mwmr_dma/include/soclib/mwmr_dma.h mwmr_dma.h file] defines all useful offsets and constants.
+||  symbolic value    || description                                         ||
+|| CHANNEL_SUCCESS    || DMA transfer successfully completed                 ||
+|| CHANNEL_ERROR_DATA || Bus error accessing the memory data buffer          ||
+|| CHANNEL_ERROR_DESC || Bus error accessing the MWMR FIFO descriptor buffer ||
+|| CHANNEL_ERROR_DATA || Bus error accessing the MWMR FIFO lock              ||
+All other values are equivalent to channel busy.
+
+For extensibility issues, you should access these registers using the offsets defined [source:trunk/soclib/soclib/module/infrastructure_component/dma_infrastructure/vci_mwmr_dma/include/soclib/mwmr_dma.h mwmr_dma.h here].
 
 This hardware component cheks for segmentation violation, and can be used as a default target.