Changes between Version 7 and Version 8 of Component/Vci Mwmr Dma

Timestamp:

Apr 9, 2015, 3:43:54 PM (9 years ago)

Author:

alain

Comment:

--

Component/Vci Mwmr Dma

@@ -24 +24 @@
 
 Each channel FSM implements two main operating modes that can be defined by software:
- * In '''MODE_DMA_IRQ''' or '''MODE_DMA_NO_IRQ''' modes the channel FSM transfer a single buffer between the memory and the coprocessor port. The number of VCI burst depends on both the memory buffer size, and the burst size. In this mode the software must define the channel configuration by writing the data buffer address and size in the channel configuration registers. When the transfer is completed, the channel FSM is blocked, waiting in the SUCCESS or ERROR state, until it is reset to IDLE state by writing a zero value in the CHANNEL_RUN register. An optional IRQ can be activated when the requested transfer is completed (only in MODE_DMA_IRQ). 
+ * In '''MODE_DMA_IRQ''' or '''MODE_DMA_NO_IRQ''', the channel FSM transfer a single buffer between the memory and the coprocessor port. The number of VCI burst depends on both the memory buffer size, and the burst size. In this mode the software must define the channel configuration by writing the data buffer address and size in the channel configuration registers, and starts the transfer by writing a non zero value in the CHANNEL_RUN register. When the transfer is completed, the channel FSM is blocked, waiting in the CHANNEL_SUCCESS or CHANNEL_ERROR state, until it is reset to IDLE state by writing a zero value in the CHANNEL_RUN register. In MODE_DMA_IRQ an IRQ is activated when the requested transfer is completed. 
 
- * In '''MWMR_MODE''', the channel FSM transfer an "infinite" data stream, between the coprocessor port and a MWMR channel (software FIFO in memory). In this mode the software must write in the channel configuration registers the data buffer address and size, but also the MWMR FIFO descriptor address and the lock address, as the channel FSM implements the 7 steps MWMR protocol.
+ * In '''MODE_MWMR''', the channel FSM transfer an "infinite" data stream, between the coprocessor port and a MWMR channel (software FIFO in memory). In this mode the software must write in the channel configuration registers the data buffer address and size, but also the MWMR FIFO descriptor address and the lock address. It starts the transfer by writing a non zero value in the CHANNEL_RUN register. The channel FSM implements an infinite loop to execute the 7 steps MWMR protocol: 
    1 - Read the ticket for queuing lock (1 flit VCI READ)
    2 - Increment atomically the ticket (VCI CAS)
@@ -34 +34 @@
    6 - Upate the status (3 flits VCI WRITE)
    7 - Release the lock (1 flit VCI WRITE)
-For an "infinite" data stream, the IRQ is not used in normal operation, and is only asserted if a VCI error is reported, ant the channel FSM is waiting in one ERROR state. 
+The IRQ is not used in normal operation. AN IRQ is asserted if a VCI error is reported, ant the channel FSM is blocked, waiting in CHANNEL_ERROR state until it is reset to IDLE state by writing a zero value in the CHANNEL_RUN register. 
 
-Several channels can simultaneously run in different modes, and the various VCI transactions corresponding to different channels are interleaved and parallelized on the VCI network. The maximum number of simultaneous VCI transactions is equal to the number of channels. 
+The various VCI transactions corresponding to different channels are interleaved and parallelized on the VCI network. The maximum number of simultaneous VCI transactions is equal to the number of channels. 
 
 Besides the communication channels, this MWMR controller provides a variable number