Changes between Version 1 and Version 2 of Component/Vci Rt Timer

Timestamp:

Oct 19, 2012, 4:42:01 PM (12 years ago)

Author:

becoulet

Comment:

--

Component/Vci Rt Timer

@@ -34 +34 @@
 ||=Name  =||=Address  =||=Direction  =||=Long name  =||=Description =||
 ||`sccnt` ||0x0  ||rw  ||Prescaler counter register  ||Prescaler counter value is decremented on rising edge of the input clock and reloaded with a configurable value when it reaches zero.  ||
-||`scrld` ||0x4  ||rw  ||Prescaler reload register  ||This register holds the reload value for the prescaler counter.  ||
+||`scrld` ||0x4  ||rw  ||Prescaler reload register  ||This register holds the reload value for the prescaler counter. The maximum value is 0xffff. ||
 ||`cfg` ||0x8  ||r  ||Device configuration register  ||This read only register holds timer component informations  ||
 ||`ctrl` ||0xc  ||rw  ||Control register  ||This register contains bits to configure various device behaviors  ||
@@ -44 +44 @@
 ||`ip` ||0x28  ||rw  ||Interrupts pending register  ||A bit is set in this register when an interrupt has been generated by the corresponding deadline. Setting a bit to one in this register clears the interrupt pending flag.  ||
 ||`copy` ||0x2c  ||w  ||Deadline copy command register  ||When bit N is written to one in this register, the associated deadline register value is overwritten with the value of the N+1 deadline register. The last deadline register can not be overwritten.  ||
+||`cancel` ||0x30  ||w  ||Deadline cancel register  ||When bit N is written to one in this register, the corresponding irq enable and pending flags are both cleared. ||
+
+  Real-time timer registers table (deadline registers)
+
 ||`dln1` ||0x80  ||rw  ||Deadline1 value register  ||This register contains lower 32 bits of the deadline value. When read, the higher 32 bits of the deadline value is latched in the rtctmp register. When written to, the deadline register higher 32 bits are set to the value of the rtctmp register.  ||
 ||`dln1s` ||0x84  ||w  ||Deadline1 set register  ||When writting to this register, the associated 64 bits deadline register is set to the sum of the timer current value and the written unsigned value.  ||