Changes between Initial Version and Version 1 of Component/Vci Simple Ram

Timestamp:

Sep 12, 2009, 1:12:50 PM (15 years ago)

Author:

alain

Comment:

--

Component/Vci Simple Ram

@@ +1 @@
+[wiki:Component SocLib Components General Index] 
+
+= !VciSimpleRam =
+
+== 1) Functional Description ==
+
+This VCI target is an embedded SRAM controller. This hardware component handles
+independent memory segments. Each segment is defined by a base address and a size (number of bytes).
+Both the base and the size parameters must be multiple of 4.
+The segments allocated to a given instance of this component are defined in the [wiki:Component/MappingTable Mapping Table].
+
+Each segment is implemented as a dynamically allocated array in the constructor.
+
+As the !VciRam component, the !VciSimpleRam component initializes its segments from a ELF binary if a
+[wiki:Component/Loader Loader] is attached to it.
+
+== 2) Component definition & usage ==
+
+source:trunk/soclib/soclib/module/internal_component/vci_simple_ram/caba/metadata/vci_simple_ram.sd
+
+See [wiki:SoclibCc/VciParameters SoclibCc/VciParameters]
+{{{
+Uses( 'vci_simple_ram', **vci_parameters )
+}}}
+
+== 3) CABA Implementation ==
+ 
+=== CABA sources ===
+
+ * interface : source:trunk/soclib/soclib/module/internal_component/vci_simple_ram/caba/source/include/vci_simple_ram.h
+ * implementation : source:trunk/soclib/soclib/module/internal_component/vci_simple_ram/caba/source/src/vci_simple_ram.cpp
+
+=== CABA Constructor parameters ===
+
+ * Uninitialized !VciSimpleRam
+{{{
+VciSimpleRam(
+     sc_module_name name,                     // Instance name
+     const soclib::common::IntTab &index,     //  Target index
+     const soclib::common::MappingTable &mt)  // Mapping Table
+}}}
+
+ * Elf-Initialized !VciSimpleRam
+You may load a binary file, by creating a loader:
+{{{
+soclib::common::Loader loader( "a.out" );
+VciSimpleRam(
+     sc_module_name name,                     // Instance name
+     const soclib::common::IntTab &index,     //  Target index
+     const soclib::common::MappingTable &mt,  // Mapping Table
+     soclib::common::Loader &loader); // Loader
+}}}
+On reset, any loadable segment in ELF file will be reloaded
+.
+=== CABA Ports ===
+
+ * sc_in<bool> '''p_resetn''' : hardware reset
+ * sc_in<bool> '''p_clk''' :  clock
+ * soclib::common::!VciTarget<vci_param> '''p_vci''' : The VCI port
+
+
+== 4)  TLM-DT Implementation ==
+
+=== TLM-DT sources ===
+
+ * interface : source:trunk/soclib/soclib/module/internal_component/vci_simple_ram/tlmdt/source/include/vci_simple_ram.h
+ * implementation : source:trunk/soclib/soclib/module/internal_component/vci_simple_ram/tlmdt/source/src/vci_simple_ram.cpp
+
+=== TLM-DT Constructor parameters ===
+{{{
+VciSimpleRam(
+     sc_module_name name,                     // Instance name
+     const soclib::common::IntTab &index,     // Target index
+     const soclib::common::MappingTable &mt,  // Mapping Table
+     soclib::common::Loader &loader);      // Loader
+}}}
+
+=== TLM-DT Ports ===
+
+ * soclib::tlmdt::!VciTarget<vci_param> '''p_vci''' : The VCI port
+