Changes between Version 2 and Version 3 of Component/Vci Vgmn

Timestamp:

May 16, 2007, 3:41:24 PM (17 years ago)

Author:

Nicolas Pouillon

Comment:

Add doc for future VGMN implementation

Component/Vci Vgmn

@@ -2 +2 @@
 
 = !VciVgmn Functional Description =
+
+[[Image(vci_vgmn.png, nolink, align=right)]]
 
 This hardware component is a generic micro-network respecting the
@@ -7 +9 @@
 simultaneous transaction, and behaves as two fully independent packet switched
 network for VCI commands and VCI responses.
+
 When several initiators try to reach the same target, the arbitration
 policy is round-robin.
@@ -36 +39 @@
 
 == Template parameters ==
+
 {{{
-template<
-     typename vci_param,   //  VCI parameters
-     size_t NB_INITIATOR,   // number of VCI initiators
-     size_t NB_TARGET,   // number of VCI targets
-     size_t MIN_LATENCY,   // minimal latency
-     size_t FIFO_DEPTH>   // network storage capacity
+template<typename vci_param>
 }}}
 
 == Constructor parameters ==
+
 {{{
 VciVgmn(
@@ -58 +58 @@
  * soclib::caba::!VciTarget<vci_param> '''p_from_initiator[NB_INITIATOR]''' : Ports from VCI initiators
  * soclib::caba::!VciInitiator<vci_param> '''p_to_target[NB_TARGET]''' : Ports to VCI targets
+
+== Implementation notes ==
+
+Each micro network (Command and Response packets interconnects) is implemented within the same
+templated code. This code is instanciated twice, once for each network.
+
+[[Image(micro_network.png, nolink, align=right)]]
+
+There is one !InputRouter object per input port, it handles incoming packets and
+forwards them to the right !OutputPortQueue.
+
+There is one !OutputPortQueue per output port, handling as many fifos as input ports,
+and one delay line. It handles putting packets on output port.