| 1 | [wiki:Component SocLib Components General Index] |
| 2 | |
| 3 | = !VciXcache Functional Description = |
| 4 | |
| 5 | This VCI initiator is a generic cache controller, fully compliant with the |
| 6 | VCI advanced protocol. Thanks to a normalized interface |
| 7 | (source:trunk/soclib/systemc/include/caba/interface/xcache_signals.h), |
| 8 | this blocking cache controller can be used by several RISC processors |
| 9 | (including Mips R3000, Sparc V8, or !OpenRisc 1000). It contains two separated |
| 10 | instruction and data caches, sharing the same VCI interface. |
| 11 | (source:trunk/soclib/systemc/include/caba/interface/vci_signals.h) |
| 12 | |
| 13 | * The VCI ADDRESS and DATA fields must have 32 bits, and the VCI ERROR field must have 1 bit. |
| 14 | * The number of lines must be a power of 2, and cannot be larger than 1024. |
| 15 | * The number of words must be a power of 2, and cannot be larger than 32. |
| 16 | |
| 17 | In order to garanty the memory consistency, this component does NOT start a new VCI transaction |
| 18 | until the previous transaction is completed. Therefore, it does not use the VCI PKTID and TRDID fields. |
| 19 | |
| 20 | Finally, this component has 4 Mealy output ports : |
| 21 | * p_icache.inst |
| 22 | * p_icache.miss |
| 23 | * p_dcache.data |
| 24 | * p_dcache.miss |
| 25 | |
| 26 | == Instruction Cache == |
| 27 | * The Instruction cache is direct mapping and read-only. |
| 28 | * It uses the [wiki:Component/MappingTable Mapping Table] to support uncached segments. |
| 29 | * In case of MISS, the processor is stalled until the missing cache line is available. |
| 30 | * The only VCI transaction generated by the Instruction cache is a read burst corresponding to a missing cache line. |
| 31 | |
| 32 | == Data Cache == |
| 33 | * The Data cache is direct mapping, and the write policy is WRITE-THROUGH (the data is immediately written in memory, and the cache is updated only in case of HIT). |
| 34 | * The data cache contains a 8 words write buffer. The cache controller builds a burst packet when there is several successive write addresses in the write buffer for the same 4 Kbytes page. |
| 35 | * It uses the [wiki:Component/MappingTable Mapping Table] to support uncached segments. |
| 36 | * The Data cache accepts a line invalidate command. |
| 37 | * In case of MISS, the processor is stalled until the missing cache line is available. |
| 38 | * Three types of VCI transactions can be generated by the data cache: |
| 39 | * read burst of fixed length, corresponding to a cached read MISS, |
| 40 | * read one word, corresponding to an uncached read, |
| 41 | * write burst of variable length, |
| 42 | * The processor is stalled in case of cached read MISS, in case of uncached read, or in case of write, if the write buffer is full. |
| 43 | |
| 44 | = !VciXcache CABA Implementation = |
| 45 | |
| 46 | The caba implementation is in |
| 47 | * source:trunk/soclib/systemc/include/caba/initiator/vci_xcache.h |
| 48 | * source:trunk/soclib/systemc/src/caba/initiator/vci_xcache.cc |
| 49 | |
| 50 | == Template parameters == |
| 51 | |
| 52 | template<typename vci_param> |
| 53 | |
| 54 | == Constructor parameters == |
| 55 | {{{ |
| 56 | VciXcache( |
| 57 | sc_module_name name, // Instance name |
| 58 | const soclib::common::MappingTable &mt, // Mapping Table |
| 59 | const soclib::common::IntTab &index, // VCI Initiator index |
| 60 | size_t WRITE_BUFFER_DEPTH, // number of requests in the write buffer |
| 61 | size_t ICACHE_LINES, // number of lines for the Icache |
| 62 | size_t ICACHE_WORDS, // number of words per line for the Icache |
| 63 | size_t DCACHE_LINES, // number of lines for the Dcache |
| 64 | size_t DCACHE_WORDS); // number or words per line for the Dcache |
| 65 | }}} |
| 66 | |
| 67 | == Ports == |
| 68 | |
| 69 | * sc_in<bool> '''p_resetn''' : Global system reset |
| 70 | * sc_in<bool> '''p_clk''' : Global system clock |
| 71 | * soclib::caba::ICacheCachePort '''p_icache''' : Icache interface |
| 72 | * soclib::caba::DCacheCachePort '''p_dcache''' : Dcache interface |
| 73 | * soclib::caba::!VciInitiator<vci_param> '''p_vci''' : The VCI port |