Changes between Initial Version and Version 1 of Component/Vci Xcache

Timestamp:

May 9, 2007, 1:29:58 PM (18 years ago)

Author:

Nicolas Pouillon

Comment:

--

Component/Vci Xcache

@@ +1 @@
+[wiki:Component SocLib Components General Index] 
+
+= !VciXcache Functional Description =
+
+This VCI initiator is a generic cache controller, fully compliant with the 
+VCI advanced protocol. Thanks to a normalized interface 
+(source:trunk/soclib/systemc/include/caba/interface/xcache_signals.h),
+this blocking cache controller can be used by several RISC processors
+(including Mips R3000, Sparc V8, or !OpenRisc 1000). It contains two separated
+instruction and data caches, sharing the same VCI interface.
+(source:trunk/soclib/systemc/include/caba/interface/vci_signals.h)
+
+ * The VCI ADDRESS and DATA fields must have 32 bits, and the VCI ERROR field must have 1 bit.
+ * The number of lines must be a power of 2, and cannot be larger than 1024.
+ * The number of words must be a power of 2, and cannot be larger than 32.
+
+In order to garanty the memory consistency, this component does NOT start a new VCI transaction
+until the previous transaction is completed. Therefore, it does not use the VCI PKTID and TRDID fields.
+
+Finally, this component has 4 Mealy output ports :
+ * p_icache.inst
+ * p_icache.miss
+ * p_dcache.data
+ * p_dcache.miss
+
+== Instruction Cache ==
+ * The Instruction cache is direct mapping and read-only.
+ * It uses the [wiki:Component/MappingTable Mapping Table] to support uncached segments.
+ * In case of MISS, the processor is stalled until the missing cache line is available.
+ * The only VCI transaction generated by the Instruction cache is a read burst corresponding to a missing cache line.
+
+== Data Cache ==
+ * The Data cache is direct mapping, and the write policy is WRITE-THROUGH (the data is immediately written in memory, and the cache is updated only in case of HIT).
+ * The data cache contains a 8 words write buffer. The cache controller builds a burst packet when there is several successive write addresses in the write buffer for the same 4 Kbytes page.
+ * It uses the [wiki:Component/MappingTable Mapping Table] to support uncached segments.
+ * The Data cache accepts a line invalidate command.
+ * In case of MISS, the processor is stalled until the missing cache line is available.
+ * Three types of VCI transactions can be generated by the data cache:
+   * read burst of fixed length, corresponding to a cached read MISS,
+   * read one word, corresponding to an uncached read,
+   * write burst of variable length,
+ * The processor is stalled in case of cached read MISS, in case of uncached read, or in case of write, if the write buffer is full.
+
+= !VciXcache CABA  Implementation =
+
+The caba implementation is in 
+ * source:trunk/soclib/systemc/include/caba/initiator/vci_xcache.h
+ * source:trunk/soclib/systemc/src/caba/initiator/vci_xcache.cc
+
+== Template parameters ==
+
+template<typename vci_param>    
+
+== Constructor parameters ==
+{{{
+VciXcache(
+     sc_module_name name,   // Instance name
+     const soclib::common::MappingTable &mt,   // Mapping Table
+     const soclib::common::IntTab &index,   //  VCI Initiator index
+     size_t WRITE_BUFFER_DEPTH,    // number of requests in the write buffer
+     size_t ICACHE_LINES,     // number of lines for the Icache
+     size_t ICACHE_WORDS,     // number of words per line for the Icache
+     size_t DCACHE_LINES,     // number of lines for the Dcache
+     size_t DCACHE_WORDS);   // number or words per line for the Dcache
+}}}
+
+== Ports ==
+
+ * sc_in<bool> '''p_resetn''' : Global system reset
+ * sc_in<bool> '''p_clk''' : Global system clock
+ * soclib::caba::ICacheCachePort '''p_icache''' : Icache interface
+ * soclib::caba::DCacheCachePort '''p_dcache''' : Dcache interface
+ * soclib::caba::!VciInitiator<vci_param> '''p_vci''' : The VCI port