Changes between Version 1 and Version 2 of Component/Vci Xcache

Timestamp:

May 17, 2007, 11:09:31 AM (17 years ago)

Author:

Nicolas Pouillon

Comment:

--

Component/Vci Xcache

@@ -31 +31 @@
 
 == Data Cache ==
+
  * The Data cache is direct mapping, and the write policy is WRITE-THROUGH (the data is immediately written in memory, and the cache is updated only in case of HIT).
- * The data cache contains a 8 words write buffer. The cache controller builds a burst packet when there is several successive write addresses in the write buffer for the same 4 Kbytes page.
+ * The data cache contains a parametrably-sized write buffer. The cache controller builds a burst packet when there is several successive write addresses in the write buffer for the same 4 Kbytes page.
  * It uses the [wiki:Component/MappingTable Mapping Table] to support uncached segments.
  * The Data cache accepts a line invalidate command.
@@ -50 +51 @@
 == Template parameters ==
 
-template<typename vci_param>    
+{{{
+template<size_t write_buffer_depth, typename vci_param>
+}}}
+
+Standard size for write buffer is 8 words.
 
 == Constructor parameters ==
 {{{
-VciXcache(
-     sc_module_name name,   // Instance name
-     const soclib::common::MappingTable &mt,   // Mapping Table
-     const soclib::common::IntTab &index,   //  VCI Initiator index
-     size_t WRITE_BUFFER_DEPTH,    // number of requests in the write buffer
-     size_t ICACHE_LINES,     // number of lines for the Icache
-     size_t ICACHE_WORDS,     // number of words per line for the Icache
-     size_t DCACHE_LINES,     // number of lines for the Dcache
-     size_t DCACHE_WORDS);   // number or words per line for the Dcache
+
+    VciXCache(
+        sc_module_name insname,
+        const soclib::common::MappingTable &mt,
+        const soclib::common::IntTab &index,
+        size_t icache_lines,
+        size_t icache_words,
+        size_t dcache_lines,
+        size_t dcache_words );
 }}}