Changes between Version 19 and Version 20 of Component/Vci Xcache

Timestamp:

Feb 11, 2008, 2:57:50 PM (16 years ago)

Author:

alain

Comment:

--

Component/Vci Xcache

@@ -22 +22 @@
  * The Instruction cache is direct mapping and read-only.
  * It uses the [wiki:Component/MappingTable Mapping Table] to support uncached segments.
- * In case of MISS, the processor is stalled until the missing cache line is available.
+ * In case of read MISS, or read uncached, the processor is stalled until the missing instruction is available.
  * The only VCI transaction generated by the Instruction cache is a read burst corresponding to a missing cache line.
 
 === Data Cache ===
 
- * The Data cache is direct mapping, and the write policy is WRITE-THROUGH (the data is immediately written in memory, and the cache is updated only in case of HIT).
- * The data cache contains a write buffer (8 words). The cache controller builds a burst packet when there are successive write requests with incrementing addresses.
+ * The Data cache is direct mapping.
+ * The write policy is WRITE-THROUGH (the data is immediately written in memory, and the cache is updated only in case of HIT).
+ * The Data cache contains a write buffer (8 words), and builds a burst when there are successive write requests with incrementing addresses.
  * It uses the [wiki:Component/MappingTable Mapping Table] to support uncached segments.
+ * The Data Cache supports the following requests : Read, Write, Linked load, and Store Conditional 
  * The Data cache accepts a line invalidate command.
- * In case of MISS, the processor is stalled until the missing cache line is available.
  * Three types of VCI transactions can be generated by the data cache:
    * read burst of fixed length, corresponding to a cached read MISS,
-   * read one word, corresponding to an uncached read,
+   * one word transaction, corresponding to an uncached read, a linked load, or a store conditional.
    * write burst of variable length,
  * The processor is stalled in case of cached read MISS, in case of uncached read, or in case of write, if the write buffer is full.