Changes between Version 6 and Version 7 of Component/Vci Xcache

Timestamp:

May 31, 2007, 9:31:18 AM (18 years ago)

Author:

Nicolas Pouillon

Comment:

--

Component/Vci Xcache

@@ -27 +27 @@
 
  * The Data cache is direct mapping, and the write policy is WRITE-THROUGH (the data is immediately written in memory, and the cache is updated only in case of HIT).
- * The data cache contains a parametrably-sized write buffer. The cache controller builds a burst packet when there is several successive write addresses in the write buffer for the same 4 Kbytes page.
+ * The data cache contains a parametrably-sized write buffer. The cache controller builds a burst packet when there are successive writes in incrementing addresses.
  * It uses the [wiki:Component/MappingTable Mapping Table] to support uncached segments.
  * The Data cache accepts a line invalidate command.
@@ -43 +43 @@
 == Usage ==
 
-!VciXcache has VCI ones and an optional write_fifo_depth defaulting to 8, it may be used like others, see [wiki:SoclibCc/VciParameters SoclibCc/VciParameters], with an additional parameter prepended.
+!VciXcache has VCI ones and an optional write_buffer_depth defaulting to 8, it may be used like others, see [wiki:SoclibCc/VciParameters SoclibCc/VciParameters], with an additional parameter prepended.
 {{{
 Uses( 'vci_xcache', **vci_parameters )
-Uses( 'vci_xcache', write_fifo_depth = 16, **vci_parameters )
+Uses( 'vci_xcache', write_buffer_depth = 16, **vci_parameters )
 }}}