Changes between Initial Version and Version 1 of Component/Vci Xcache Wrapper

Timestamp:

Jun 10, 2008, 12:35:41 AM (16 years ago)

Author:

alain

Comment:

--

Component/Vci Xcache Wrapper

@@ +1 @@
+[wiki:Component SocLib Components General Index] 
+
+= !VciXcacheWrapper =
+
+== 1) Functional Description ==
+
+This VCI initiator is a generic cache controller, fully compliant with the 
+VCI advanced protocol. This hardware component can be used to interface any
+32 bits RISC processor (such as Mips R3000, Sparc V8, or PPC 405) to a VCI based multi-processor system.
+It acts directly as a wrapper for any ISS (Instruction Set Simulator) respecting the standardized API
+defined [wiki:WritingRules/RISC here].
+
+This cache controller implements two separated instruction and data caches, sharing the same VCI interface.
+
+It provides the same functionalities as the previous VciXcache component, with an higher simulation speed,
+an full support for associativity (for both the instruction and data caches).
+
+ * The VCI ADDRESS and DATA fields must have 32 bits, and the VCI ERROR field has 1 bit.
+ * The number of lines must be a power of 2, and cannot be larger than 1024.
+ * The number of words must be a power of 2, and cannot be larger than 32.
+ * The number of associativity levels must be a power of 2, and cannot be larger than 16.
+
+In order to garanty the memory consistency, this component does NOT start a new VCI transaction
+until the previous transaction is completed. Therefore, it does not use the VCI PKTID and TRDID fields.
+
+=== Instruction Cache ===
+
+ * It is read-only.
+ * It uses the [wiki:Component/MappingTable Mapping Table] to support uncached segments.
+ * In case of read MISS, or read uncached, the processor is stalled until the missing instruction is available.
+ * The only VCI transaction generated by the Instruction cache is a read burst corresponding to a missing cache line.
+
+=== Data Cache ===
+
+ * The write policy is WRITE-THROUGH (the data is immediately written in memory, and the cache is updated only in case of HIT).
+ * The Data cache contains a write buffer (8 words), and builds a burst when there are successive write requests with incrementing addresses.
+ * It uses the [wiki:Component/MappingTable Mapping Table] to support uncached segments.
+ * The Data Cache supports the following requests : Read, Write, Linked load, and Store Conditional 
+ * The Data cache accepts a line invalidate command.
+ * Three types of VCI transactions can be generated by the data cache:
+   * read burst of fixed length, corresponding to a cached read MISS,
+   * one word transaction, corresponding to an uncached read, a linked load, or a store conditional.
+   * write burst of variable length,
+ * The processor is stalled in case of cached read MISS, in case of uncached read, or in case of write, if the write buffer is full.
+
+== 2) Component definition & usage ==
+
+source:trunk/soclib/soclib/module/internal_component/vci_xcache/caba/metadata/vci_xcache_wrapper.sd
+
+== 3) CABA  Implementation ==
+
+ * interface : source:trunk/soclib/soclib/module/internal_component/vci_xcache/caba/source/include/vci_xcache_wrapper.h
+ * implementation : source:trunk/soclib/soclib/module/internal_component/vci_xcache/caba/source/src/vci_xcache_wrapper.cpp
+
+=== CABA template parameters ===
+
+This component has two template parameters, defining respectively the width of the various VCI signals,
+and the instanciated ISS.
+{{{
+template<typename vci_param, typename iss_t>
+}}}
+
+=== CABA constructor parameters ===
+{{{
+
+    VciXcacheWrapper(
+        sc_module_name insname, 
+        int proc_id,
+        const soclib::common::MappingTable &mt,
+        const soclib::common::IntTab &index,
+        size_t icache_lines,
+        size_t icache_words,
+        size_t icache_sets,
+        size_t dcache_lines,
+        size_t dcache_words 
+        size_t dcache_sets );
+}}}
+
+=== CABA ports ===
+
+ * sc_in<bool> '''p_resetn''' : Global system reset
+ * sc_in<bool> '''p_clk''' : Global system clock
+ * soclib::caba::!VciInitiator<vci_param> '''p_vci''' : The VCI port
+
+== 4) TLM-T Implementation ==
+
+ * interface : source:trunk/soclib/soclib/module/internal_component/vci_xcache/tlmt/source/include/vci_xcache_wrapper.h
+ * implementation : source:trunk/soclib/soclib/module/internal_component/vci_xcache/tlmt/source/src/vci_xcache_wrapper.cpp
+
+=== TLM-T template parameters ===
+
+=== TLM-T constructor parameters ===
+
+=== TLM-T ports ===
+
+