Changes between Version 9 and Version 10 of Component/Vci Xcache Wrapper

Timestamp:

Aug 25, 2008, 5:42:23 PM (16 years ago)

Author:

alain

Comment:

--

Component/Vci Xcache Wrapper

@@ -9 +9 @@
 32 bits RISC processor (such as Mips32, Sparc V8, Xilinx microBlaze, Altera Nios, or PPC 405) to a VCI based multi-processor system.
 They act directly as a wrapper for any ISS (Instruction Set Simulator) respecting the standardized API
-defined [wiki:WritingRules/RISC here].
+defined the[source:root/trunk/soclib/soclib/lib/iss2/include/iss2.h here].
 
 Each cache controller implements two separated instruction and data caches, sharing the same VCI interface.
@@ -60 +60 @@
 === Generic MMU ===
 
-The Vcache and CC_Vcache components implement a generic MMU service, that can be used by all the single instruction issue 32 bits processors available in the SoCLib platform.
+The Vcache and CC_Vcache components implement a generic MMU, that can be used by all the single instruction issue 32 bits processors available in the SoCLib platform.
+
+The generic MMU defines 10 registers, that can be accessed by the software ttrough the generic cache/proccessor interface defined
 In the Vcache and CC_Vcache components, the cachability (for both instruction & data accesses) can be defined 
 by software - on a per-logical-page basis) through the cacheability attribut contained in each page descriptor.