Changes between Version 10 and Version 11 of Component/Vci Xcache Wrapper
- Timestamp:
- Aug 25, 2008, 5:57:20 PM (16 years ago)
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Component/Vci Xcache Wrapper
v10 v11 9 9 32 bits RISC processor (such as Mips32, Sparc V8, Xilinx microBlaze, Altera Nios, or PPC 405) to a VCI based multi-processor system. 10 10 They act directly as a wrapper for any ISS (Instruction Set Simulator) respecting the standardized API 11 defined the[source:root/trunk/soclib/soclib/lib/iss2/include/iss2.h here].11 defined in source:root/trunk/soclib/soclib/lib/iss2/include/iss2.h. 12 12 13 13 Each cache controller implements two separated instruction and data caches, sharing the same VCI interface. … … 63 63 64 64 The generic MMU defines 10 registers, that can be accessed by the software ttrough the generic cache/proccessor interface defined 65 :|| PTPR || set Page Table Pointer Register || Write |||| TLB_EN || activates Data & Instruction TLBs || Write || || ICACHE_FLUSH || flush Instruction Cache || Write |||| DCACHE_FLUSH || flush Data Cache || Write |||| ITLB_INVAL || Instruction TLB line invalidate || Write |||| DTLB_INVAL || Data TLB line invalidate || Write |||| ICACHE_INVAL || Instruction Cache line invalidate|| Write |||| DCACHE_INVAL || Data Cache line invalidate|| Write |||| BAD_VADDR || Bad Virtual Address Register || Read |||| ERR_TYPE || Exception type Register || Read ||In the Vcache and CC_Vcache components, the cachability (for both instruction & data accesses) can be defined by software - on a per-logical-page basis) through the cacheability 65 66 In the Vcache and CC_Vcache components, the cachability (for both instruction & data accesses) can be defined 66 67 by software - on a per-logical-page basis) through the cacheability attribut contained in each page descriptor.