Changes between Version 10 and Version 11 of Component/Vci Xcache Wrapper

Timestamp:

Aug 25, 2008, 5:57:20 PM (18 years ago)

Author:

alain

Comment:

--

Component/Vci Xcache Wrapper

@@ -9 +9 @@
 32 bits RISC processor (such as Mips32, Sparc V8, Xilinx microBlaze, Altera Nios, or PPC 405) to a VCI based multi-processor system.
 They act directly as a wrapper for any ISS (Instruction Set Simulator) respecting the standardized API
-defined the[source:root/trunk/soclib/soclib/lib/iss2/include/iss2.h here].
+defined in source:root/trunk/soclib/soclib/lib/iss2/include/iss2.h.
 
 Each cache controller implements two separated instruction and data caches, sharing the same VCI interface.
@@ -63 +63 @@
 
 The generic MMU defines 10 registers, that can be accessed by the software ttrough the generic cache/proccessor interface defined
+:|| PTPR     || set Page Table Pointer Register   || Write |||| TLB_EN         || activates Data & Instruction TLBs  || Write || || ICACHE_FLUSH || flush Instruction Cache         || Write |||| DCACHE_FLUSH || flush Data Cache         || Write |||| ITLB_INVAL || Instruction TLB line invalidate || Write |||| DTLB_INVAL || Data TLB line invalidate         || Write |||| ICACHE_INVAL || Instruction Cache line invalidate|| Write |||| DCACHE_INVAL || Data Cache line invalidate|| Write |||| BAD_VADDR || Bad Virtual Address Register   || Read |||| ERR_TYPE         || Exception type Register || Read ||In the Vcache and CC_Vcache components, the cachability (for both instruction & data accesses) can be defined by software - on a per-logical-page basis) through the cacheability 
 In the Vcache and CC_Vcache components, the cachability (for both instruction & data accesses) can be defined 
 by software - on a per-logical-page basis) through the cacheability attribut contained in each page descriptor.