Changes between Version 11 and Version 12 of Component/Vci Xcache Wrapper

Timestamp:

Aug 25, 2008, 6:31:39 PM (16 years ago)

Author:

alain

Comment:

--

Component/Vci Xcache Wrapper

@@ -61 +61 @@
 
 The Vcache and CC_Vcache components implement a generic MMU, that can be used by all the single instruction issue 32 bits processors available in the SoCLib platform.
-
-The generic MMU defines 10 registers, that can be accessed by the software ttrough the generic cache/proccessor interface defined
-:|| PTPR     || set Page Table Pointer Register   || Write |||| TLB_EN         || activates Data & Instruction TLBs  || Write || || ICACHE_FLUSH || flush Instruction Cache         || Write |||| DCACHE_FLUSH || flush Data Cache         || Write |||| ITLB_INVAL || Instruction TLB line invalidate || Write |||| DTLB_INVAL || Data TLB line invalidate         || Write |||| ICACHE_INVAL || Instruction Cache line invalidate|| Write |||| DCACHE_INVAL || Data Cache line invalidate|| Write |||| BAD_VADDR || Bad Virtual Address Register   || Read |||| ERR_TYPE         || Exception type Register || Read ||In the Vcache and CC_Vcache components, the cachability (for both instruction & data accesses) can be defined by software - on a per-logical-page basis) through the cacheability 
+This MMU performs both the logical address to physical address translation, and access rights checking.
+ * The logical address is 32 bits.
+ * The Physical address is 36 bits (or less).
+ * It is implemented as a two level, hierarchical, page table. 
+ * Both first & second level page table contains 1024 entries. 
+ * Two page sizes are supported : 4 Kbytes, or 4 Mbytes.
+ * Two separated TLBs are iused for instruction and data addresses.
+ * The TLB misses are handled by hardware (hardwired table-walk).
+ * An execution context is defined by the value stored in the PTPR (Page Table Pointer Register). 
+ * Any context switch flush both the instruction & data TLBs.
+
+The page page descriptor format is 32 bits:
+
+||ET ||  Entry Type                                            || 2 bits  ||
+||C   || Cachable                                               || 1 bit    ||
+||W  || Writable                                                 || 1 bit    ||
+||X   || eXecutable                                            || 1 bit    ||
+||U   || User 'access in user mode allowed  || 1 bit    ||
+||G   || Global (not invalidate by TLB flush  || 1 bit    ||
+||D   || Dirty  (page has been modified)       || 1 bit    ||
+||PPN||Physical Page Number                        || 24 bits ||
+
+The generic MMU defines 10 registers, that can be accessed by the software ttrough the generic cache/proccessor interface defined in source:root/trunk/soclib/soclib/lib/iss2/include/iss2.h
+
+|| PTPR                   || set Page Table Pointer Register     || Write ||
+|| TLB_EN               || activates Data & Instruction TLBs  || Write || 
+|| ICACHE_FLUSH  || flush Instruction Cache                   || Write ||
+|| DCACHE_FLUSH || flush Data Cache                              || Write ||
+|| ITLB_INVAL         || Instruction TLB line invalidate       || Write ||
+|| DTLB_INVAL       || Data TLB line invalidate                  || Write ||
+|| ICACHE_INVAL  || Instruction Cache line invalidate   || Write ||
+|| DCACHE_INVAL || Data Cache line invalidate             || Write ||
+|| BAD_VADDR      || Bad Virtual Address Register         || Read ||
+|| ERR_TYPE           || Exception type Register                  || Read ||
+
 In the Vcache and CC_Vcache components, the cachability (for both instruction & data accesses) can be defined 
 by software - on a per-logical-page basis) through the cacheability attribut contained in each page descriptor.