Changes between Version 12 and Version 13 of Component/Vci Xcache Wrapper


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Timestamp:
Aug 25, 2008, 6:44:32 PM (16 years ago)
Author:
alain
Comment:

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  • Component/Vci Xcache Wrapper

    v12 v13  
    88VCI advanced protocol. They  can be used to interface any - single instruction issue -
    9932 bits RISC processor (such as Mips32, Sparc V8, Xilinx microBlaze, Altera Nios, or PPC 405) to a VCI based multi-processor system.
    10 They act directly as a wrapper for any ISS (Instruction Set Simulator) respecting the standardized API
    11 defined in source:root/trunk/soclib/soclib/lib/iss2/include/iss2.h.
     10They act directly as a wrapper for any ISS (Instruction Set Simulator) respecting the generic cache/processor interface defined in source:root/trunk/soclib/soclib/lib/iss2/include/iss2.h.
    1211
    1312Each cache controller implements two separated instruction and data caches, sharing the same VCI interface.
    14 
    1513
    1614 * The !VciXcacheWrapper (in short Xcache) replace the previous !VciXcache component. It has an higher simulation speed, and supports  associativity (for both the instruction and data caches).
     
    6765 * Both first & second level page table contains 1024 entries.
    6866 * Two page sizes are supported : 4 Kbytes, or 4 Mbytes.
    69  * Two separated TLBs are iused for instruction and data addresses.
     67 * Two separated TLBs are used for instruction and data addresses.
    7068 * The TLB misses are handled by hardware (hardwired table-walk).
    7169 * An execution context is defined by the value stored in the PTPR (Page Table Pointer Register).
     
    8381||PPN||Physical Page Number                        || 24 bits ||
    8482
    85 The generic MMU defines 10 registers, that can be accessed by the software ttrough the generic cache/proccessor interface defined in source:root/trunk/soclib/soclib/lib/iss2/include/iss2.h
     83The generic MMU defines 10 registers, that can be accessed by the software through the generic cache/proccessor interface defined in source:root/trunk/soclib/soclib/lib/iss2/include/iss2.h
    8684
    8785|| PTPR                   || set Page Table Pointer Register     || Write ||
     
    9593|| BAD_VADDR      || Bad Virtual Address Register         || Read ||
    9694|| ERR_TYPE           || Exception type Register                  || Read ||
     95
     96Both the instruction & data caches are accessed with physical addresses.
    9797
    9898In the Vcache and CC_Vcache components, the cachability (for both instruction & data accesses) can be defined
     
    145145        const soclib::common::MappingTable &mt,
    146146        const soclib::common::IntTab &index,
    147         size_t icache_lines,
    148         size_t icache_words,
    149         size_t icache_sets,
    150         size_t dcache_lines,
    151         size_t dcache_words 
    152         size_t dcache_sets );
     147        size_t icache_sets,        // number of  associative sets (instruction cache)
     148        size_t icache_words,    // number of words per line (instruction cache)
     149        size_t icache_ways,      // number of ways per associative set (instruction cache)
     150        size_t dcache_sets,       // number of  associative sets (data cache)
     151        size_t dcache_words,    // number of words per line (data cache)
     152        size_t dcache_ways );    // number of ways per associative set (data cache)
    153153}}}
    154154'''Vcache'''
     
    219219=== CABA ports ===
    220220
     221'''Xcache''' & '''Vcache'''
    221222 * sc_in<bool> '''p_resetn''' : Global system reset
    222223 * sc_in<bool> '''p_clk''' : Global system clock
    223224 * soclib::caba::!VciInitiator<vci_param> '''p_vci''' : The VCI port
    224225
     226'''CC_Xcache''' & '''CC_Vcache'''
     227 * sc_in<bool> '''p_resetn''' : Global system reset
     228 * sc_in<bool> '''p_clk''' : Global system clock
     229 * soclib::caba::!VciInitiator<vci_param> '''p_vci_ini''' : The VCI initiator port
     230 * soclib::caba::!VciTarget<vci_param> '''p_vci_tgt''' : The VCI target port
    225231== 3) TLM-T Implementation ==
    226232