Changes between Version 12 and Version 13 of Component/Vci Xcache Wrapper
- Timestamp:
- Aug 25, 2008, 6:44:32 PM (16 years ago)
Legend:
- Unmodified
- Added
- Removed
- Modified
-
Component/Vci Xcache Wrapper
v12 v13 8 8 VCI advanced protocol. They can be used to interface any - single instruction issue - 9 9 32 bits RISC processor (such as Mips32, Sparc V8, Xilinx microBlaze, Altera Nios, or PPC 405) to a VCI based multi-processor system. 10 They act directly as a wrapper for any ISS (Instruction Set Simulator) respecting the standardized API 11 defined in source:root/trunk/soclib/soclib/lib/iss2/include/iss2.h. 10 They act directly as a wrapper for any ISS (Instruction Set Simulator) respecting the generic cache/processor interface defined in source:root/trunk/soclib/soclib/lib/iss2/include/iss2.h. 12 11 13 12 Each cache controller implements two separated instruction and data caches, sharing the same VCI interface. 14 15 13 16 14 * The !VciXcacheWrapper (in short Xcache) replace the previous !VciXcache component. It has an higher simulation speed, and supports associativity (for both the instruction and data caches). … … 67 65 * Both first & second level page table contains 1024 entries. 68 66 * Two page sizes are supported : 4 Kbytes, or 4 Mbytes. 69 * Two separated TLBs are iused for instruction and data addresses.67 * Two separated TLBs are used for instruction and data addresses. 70 68 * The TLB misses are handled by hardware (hardwired table-walk). 71 69 * An execution context is defined by the value stored in the PTPR (Page Table Pointer Register). … … 83 81 ||PPN||Physical Page Number || 24 bits || 84 82 85 The generic MMU defines 10 registers, that can be accessed by the software t trough the generic cache/proccessor interface defined in source:root/trunk/soclib/soclib/lib/iss2/include/iss2.h83 The generic MMU defines 10 registers, that can be accessed by the software through the generic cache/proccessor interface defined in source:root/trunk/soclib/soclib/lib/iss2/include/iss2.h 86 84 87 85 || PTPR || set Page Table Pointer Register || Write || … … 95 93 || BAD_VADDR || Bad Virtual Address Register || Read || 96 94 || ERR_TYPE || Exception type Register || Read || 95 96 Both the instruction & data caches are accessed with physical addresses. 97 97 98 98 In the Vcache and CC_Vcache components, the cachability (for both instruction & data accesses) can be defined … … 145 145 const soclib::common::MappingTable &mt, 146 146 const soclib::common::IntTab &index, 147 size_t icache_ lines,148 size_t icache_words, 149 size_t icache_ sets,150 size_t dcache_ lines,151 size_t dcache_words 152 size_t dcache_ sets );147 size_t icache_sets, // number of associative sets (instruction cache) 148 size_t icache_words, // number of words per line (instruction cache) 149 size_t icache_ways, // number of ways per associative set (instruction cache) 150 size_t dcache_sets, // number of associative sets (data cache) 151 size_t dcache_words, // number of words per line (data cache) 152 size_t dcache_ways ); // number of ways per associative set (data cache) 153 153 }}} 154 154 '''Vcache''' … … 219 219 === CABA ports === 220 220 221 '''Xcache''' & '''Vcache''' 221 222 * sc_in<bool> '''p_resetn''' : Global system reset 222 223 * sc_in<bool> '''p_clk''' : Global system clock 223 224 * soclib::caba::!VciInitiator<vci_param> '''p_vci''' : The VCI port 224 225 226 '''CC_Xcache''' & '''CC_Vcache''' 227 * sc_in<bool> '''p_resetn''' : Global system reset 228 * sc_in<bool> '''p_clk''' : Global system clock 229 * soclib::caba::!VciInitiator<vci_param> '''p_vci_ini''' : The VCI initiator port 230 * soclib::caba::!VciTarget<vci_param> '''p_vci_tgt''' : The VCI target port 225 231 == 3) TLM-T Implementation == 226 232