Changes between Version 15 and Version 16 of Component/Vci Xcache Wrapper

Timestamp:

Aug 26, 2008, 4:21:19 PM (16 years ago)

Author:

alain

Comment:

--

Component/Vci Xcache Wrapper

@@ -85 +85 @@
 The generic MMU defines 10 registers, that can be accessed by the software through the generic cache/proccessor interface defined in source:root/trunk/soclib/soclib/lib/iss2/include/iss2.h
 
-|| PTPR                   || set Page Table Pointer Register     || Write ||
-|| TLB_EN               || activates Data & Instruction TLBs  || Write || 
-|| ICACHE_FLUSH  || flush Instruction Cache                   || Write ||
-|| DCACHE_FLUSH || flush Data Cache                              || Write ||
-|| ITLB_INVAL         || Instruction TLB line invalidate       || Write ||
-|| DTLB_INVAL       || Data TLB line invalidate                  || Write ||
-|| ICACHE_INVAL  || Instruction Cache line invalidate   || Write ||
-|| DCACHE_INVAL || Data Cache line invalidate             || Write ||
-|| BAD_VADDR      || Bad Virtual Address Register         || Read ||
-|| ERR_TYPE           || Exception type Register                  || Read ||
+|| PTPR                   || set Page Table Pointer Register        || Write ||
+|| TLB_EN               || set Data & Inst TLBs Mode Register  || Write || 
+|| ICACHE_FLUSH  || Instruction Cache flush                     || Write ||
+|| DCACHE_FLUSH || Data Cache flush                                || Write ||
+|| ITLB_INVAL         || Instruction TLB line invalidate          || Write ||
+|| DTLB_INVAL       || Data TLB line invalidate                     || Write ||
+|| ICACHE_INVAL  || Instruction Cache line invalidate       || Write ||
+|| DCACHE_INVAL || Data Cache line invalidate                 || Write ||
+|| BAD_VADDR      || Bad Virtual Address Register             || Read ||
+|| ERR_TYPE           || Exception type Register                      || Read ||
 
 Both the instruction & data caches are accessed with physical addresses.