71 | | * An execution context is defined by the value stored in the PTPR (Page Table Pointer Register). |
72 | | * Any context switch flush both the instruction & data TLBs. |
73 | | |
74 | | The page page descriptor format is 32 bits: |
75 | | |
76 | | ||ET || Entry Type || 2 bits || |
77 | | ||C || Cachable || 1 bit || |
78 | | ||W || Writable || 1 bit || |
79 | | ||X || eXecutable || 1 bit || |
80 | | ||U || User 'access in user mode allowed || 1 bit || |
81 | | ||G || Global (not invalidate by TLB flush || 1 bit || |
82 | | ||D || Dirty (page has been modified) || 1 bit || |
83 | | ||PPN||Physical Page Number || 24 bits || |
84 | | |
85 | | The generic MMU defines 10 registers, that can be accessed by the software through the generic cache/proccessor interface defined in source:root/trunk/soclib/soclib/lib/iss2/include/iss2.h |
86 | | |
87 | | || PTPR || set Page Table Pointer Register || Write || |
88 | | || TLB_EN || set Data & Inst TLBs Mode Register || Write || |
89 | | || ICACHE_FLUSH || Instruction Cache flush || Write || |
90 | | || DCACHE_FLUSH || Data Cache flush || Write || |
91 | | || ITLB_INVAL || Instruction TLB line invalidate || Write || |
92 | | || DTLB_INVAL || Data TLB line invalidate || Write || |
93 | | || ICACHE_INVAL || Instruction Cache line invalidate || Write || |
94 | | || DCACHE_INVAL || Data Cache line invalidate || Write || |
95 | | || BAD_VADDR || Bad Virtual Address Register || Read || |
96 | | || ERR_TYPE || Exception type Register || Read || |
97 | | |
98 | | Both the instruction & data caches are accessed with physical addresses. |
99 | | |
100 | | In the Vcache and CC_Vcache components, the cachability (for both instruction & data accesses) can be defined |
101 | | by software - on a per-logical-page basis) through the cacheability attribut contained in each page descriptor. |
102 | | But the cachability can also be controlled (on a per-physical-segment basis) through the mapping table. |
| 69 | |
| 70 | A more detailed specification of the generic MMU can be find on the Web site of the TSAR project : |
| 71 | [https://www-asim.lip6.fr/trac/tsar/wiki/VirtualMemory] |