Changes between Version 22 and Version 23 of Component/Vci Xcache Wrapper

Timestamp:

Oct 27, 2009, 3:51:15 PM (15 years ago)

Author:

alinevieiramello@…

Comment:

--

Component/Vci Xcache Wrapper

@@ -191 +191 @@
  * soclib::caba::!VciTarget<vci_param> '''p_vci_tgt''' : The VCI target port
 
-== 3) TLM-T Implementation ==
-
- * interface : source:trunk/soclib/soclib/module/internal_component/vci_xcache_wrapper/tlmt/source/include/vci_xcache_wrapper.h
- * implementation : source:trunk/soclib/soclib/module/internal_component/vci_xcache_wrapper/tlmt/source/src/vci_xcache_wrapper.cpp
+== 3) TLM-DT Implementation ==
+
+ * interface : source:trunk/soclib/soclib/module/internal_component/vci_xcache_wrapper/tlmdt/source/include/vci_xcache_wrapper.h
+ * implementation : source:trunk/soclib/soclib/module/internal_component/vci_xcache_wrapper/tlmdt/source/src/vci_xcache_wrapper.cpp
 
 === TLM-T template parameters ===
 
-=== TLM-T constructor parameters ===
-
-=== TLM-T ports ===
-
-
+All these components have two template parameters, defining respectively the width of the various VCI signals,
+and the instanciated ISS.
+{{{
+template<typename vci_param, typename iss_t>
+}}}
+
+=== TLM-DT constructor parameters ===
+
+'''Xcache''' 
+{{{
+    VciXcacheWrapper(
+        sc_module_name insname, 
+        int proc_id,
+        const soclib::common::MappingTable &mt,
+        const soclib::common::IntTab &index,
+        size_t icache_ways,  // number of ways per associative set (instruction cache)
+        size_t icache_sets,  // number of  associative sets (instruction cache)
+        size_t icache_words,  // number of words per line (instruction cache)
+        size_t dcache_ways,  // number of ways per associative set (data cache) 
+        size_t dcache_sets,  // number of  associative sets (data cache)
+        size_t dcache_words);  // number of words per line (data cache)
+or
+    VciXcacheWrapper(
+        sc_module_name insname, 
+        int proc_id,
+        const soclib::common::MappingTable &mt,
+        const soclib::common::IntTab &index,
+        size_t icache_ways,  // number of ways per associative set (instruction cache)
+        size_t icache_sets,  // number of  associative sets (instruction cache)
+        size_t icache_words,  // number of words per line (instruction cache)
+        size_t dcache_ways,  // number of ways per associative set (data cache) 
+        size_t dcache_sets,  // number of  associative sets (data cache)
+        size_t dcache_words,  // number of words per line (data cache)
+        size_t time_quantum); // maximal number of cycles between two consecutive messages (default = 100 cycles)
+
+}}}
+
+
+=== TLM-DT ports ===
+'''Xcache'''
+ * tlm::tlm_initiator_socket<32, tlm::tlm_base_protocol_types> p_vci_initiator;   // VCI initiator port
+ * std::vector<tlm_utils::simple_target_socket_tagged<VciXcacheWrapper,32,tlm::tlm_base_protocol_types> *> p_irq_target; // IRQ target port