Changes between Version 29 and Version 30 of Component/Vci Xcache Wrapper


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Timestamp:
Jan 17, 2010, 12:10:35 PM (14 years ago)
Author:
alain
Comment:

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  • Component/Vci Xcache Wrapper

    v29 v30  
    88VCI advanced protocol. They  can be used to interface any - single instruction issue -
    9932 bits RISC processor (such as Mips32, Sparc V8, Xilinx microBlaze, Altera Nios, or PPC 405) to a VCI based multi-processor system.
    10 They act directly as a wrapper for any ISS (Instruction Set Simulator) respecting the generic cache/processor interface defined in source:root/trunk/soclib/soclib/lib/iss2/include/iss2.h.
     10They act directly as a wrapper for any ISS (Instruction Set Simulator) respecting the generic cache/processor interface defined in source:root/trunk/soclib/soclib/iss/iss2/include/iss2.h.
    1111
    1212Each cache controller implements two separated instruction and data caches, sharing the same VCI interface.