Changes between Version 30 and Version 31 of Component/Vci Xcache Wrapper


Ignore:
Timestamp:
Jan 17, 2010, 12:15:27 PM (15 years ago)
Author:
alain
Comment:

--

Legend:

Unmodified
Added
Removed
Modified

  • Component/Vci Xcache Wrapper

    v30 v31  
    88VCI advanced protocol. They  can be used to interface any - single instruction issue -
    9932 bits RISC processor (such as Mips32, Sparc V8, Xilinx microBlaze, Altera Nios, or PPC 405) to a VCI based multi-processor system.
    10 They act directly as a wrapper for any ISS (Instruction Set Simulator) respecting the generic cache/processor interface defined in source:root/trunk/soclib/soclib/iss/iss2/include/iss2.h.
     10They act directly as a wrapper for any ISS (Instruction Set Simulator) respecting the generic cache/processor interface defined in source:trunk/soclib/soclib/iss/iss2/include/iss2.h.
    1111
    1212Each cache controller implements two separated instruction and data caches, sharing the same VCI interface.