Changes between Version 31 and Version 32 of Component/Vci Xcache Wrapper


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Timestamp:
Jan 9, 2011, 6:53:38 PM (13 years ago)
Author:
alain
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  • Component/Vci Xcache Wrapper

    v31 v32  
    11[wiki:Component SocLib Components General Index]
    22
    3 = !VciXcacheWrapper /  !VciVcacheWrapper / !VciCcXcacheWrapper / !VciCcVcacheWrapper =
     3= !VciXcacheWrapper /  !VciVcacheWrapper =
    44
    55== 1) Functional Description ==
    66
    7 These 4 hardware components are generic cache controllers, fully compliant with the
     7These 2 hardware components are generic cache controllers, fully compliant with the
    88VCI advanced protocol. They  can be used to interface any - single instruction issue -
    9932 bits RISC processor (such as Mips32, Sparc V8, Xilinx microBlaze, Altera Nios, or PPC 405) to a VCI based multi-processor system.
    … …  
    1313
    1414 * The !VciXcacheWrapper (in short Xcache) replace the previous !VciXcache component. It has an higher simulation speed, and supports  associativity (for both the instruction and data caches).
    15  * The !VciVcacheWrapper (in short Vcache) has the same functionnalities as the Xcache, and implements a generic paged MMU (see below).
    16  * The !VciCcacheWrapper (in short CC_Xcache) has the same functionnalities as the Xcache, and implement a directory-based cache coherence protocol (see below).
    17  * The !VciCcVcachewrapper supports both the generic MMU and the cache coherence.
    18  
    19 ||                                        || No Virtual memory    || With Virtual Memory   ||
    20 ||No Cache Coherence   || !VciXcacheWrapper     || !VciVcacheWrapper     ||
    21 ||With Cache Coherence|| !VciCcXcacheWrapper || !VciCcVcacheWrapper ||
     15 * The !VciVcacheWrapper (in short Vcache) has the same functionnalities as the Xcache, and implements a generic paged MMU.
    2216
    2317=== General features ===
    … …  
    2620 * The VCI DATA field must have 4 bytes,
    2721 * The VCI ADDRESS field must have 32 bits (when there is no MMU),
    28  * The VCI PLEN field must be large enough to represent 4*(N+2), where N is the number of words per cache line.
     22 * The VCI PLEN field must be large enough to represent 4*(N+2), where N is the number of words in a cache line.
    2923 * The VCI ERROR field has 1 bit.
    3024 * The number of lines must be a power of 2, and cannot be larger than 1024.
    … …  
    4236 * It uses the [wiki:Component/MappingTable Mapping Table] to support uncached segments.
    4337 * In case of read MISS, or read uncached, the processor is stalled until the missing instruction is available.
    44  * The only VCI transaction generated by the Instruction cache is a read burst corresponding to a missing cache line.
     38 * The two VCI transactions generated by the Instruction cache are
     39   * read burst corresponding to a missing cache line,
     40   * one word read, when the corresponding address is uncached.
    4541
    4642=== Data Cache ===
    … …  
    5248 * The Data cache accepts a line invalidate command.
    5349 * Three types of VCI transactions can be generated by the data cache:
    54    * read burst of fixed length, corresponding to a cached read MISS,
     50   * read burst, corresponding to a missing cache line,
    5551   * one word transaction, corresponding to an uncached read, a linked load, or a store conditional.
    5652   * write burst of variable length ( no larger than a cache line)
    … …  
    6965 
    7066A more detailed specification of the generic MMU can be find on the Web site of the TSAR project :
    71 [https://www-asim.lip6.fr/trac/tsar/wiki/VirtualMemory]
    72  
    73 === Cache Coherence ===
    74 
    75 The CC_Xcache & CC_Vcache components implement a directory-based cache coherence protocol.
    76 The global memory directory itself should be implemented in a dedicated memory controller such as the !VciMemCache component.
    77 The cache coherence protocol is strongly simplified by the WRITE-THROUGH policy and is implemented by three types of packets.
    78 The CC_Xcache (or CC_Vcache) component has one VCI target port, and can receive UPDATE or INVALIDATE packets, from the memory controller. When the CC-Xcache (or CC_Vcache) component discard a cache line (due to a cache line replacement following a MISS), it signals this change by a CLEANUP packet sent to the cache controller. All those ''coherence'' packets are implemented as VCI write packets to dedicated memory mapped registers.
    79  * an UPDATE packet (memory controller to cache) has N+2 words : the first word contains the the line index of the modified cache line. The second word contains the index of the first modified word in the line. The N following words contain the N data values.
    80  * an INVALIDATE packet (memory controller to cache) has 1 word : it contains the line index of the modified cache line.
    81  * a CLEANUP packet (cache to memory controller) has 1 word : it contains the line index of the discarded cache line.
     67[https://www-asim.lip6.fr/trac/tsar/wiki/VirtualMemory]
    8268
    8369== 2) CABA  Implementation ==
    … …  
    9278 * implementation : source:trunk/soclib/soclib/module/internal_component/vci_vcache_wrapper/caba/source/src/vci_vcache_wrapper.cpp
    9379'''CC_Xcache'''
    94  * Usage : source:trunk/soclib/soclib/module/internal_component/vci_cc_xcache_wrapper/caba/metadata/vci_cc_xcache_wrapper.sd
    95  * interface : source:trunk/soclib/soclib/module/internal_component/vci_cc_xcache_wrapper/caba/source/include/vci_cc_xcache_wrapper.h
    96  * implementation : source:trunk/soclib/soclib/module/internal_component/vci_cc_xcache_wrapper/caba/source/src/vci_cc_xcache_wrapper.cpp
    97 '''CC_Vcache'''
    98  * Usage : source:trunk/soclib/soclib/module/internal_component/vci_cc_vcache_wrapper/caba/metadata/vci_cc_vcache_wrapper.sd
    99  * interface : source:trunk/soclib/soclib/module/internal_component/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
    100  * implementation : source:trunk/soclib/soclib/module/internal_component/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
    10180
    10281=== CABA template parameters ===
    10382
    104 All these 4 component have two template parameters, defining respectively the width of the various VCI signals,
     83Both the Xcache and Vcache components have two template parameters, defining respectively the width of the various VCI signals,
    10584and the instanciated ISS.
    10685{{{
    … …  
    141120        size_t dcache_sets,  // number of  associative sets (data cache)
    142121        size_t dcache_words);  // number of words per line (data cache)
    143 }}}
    144 '''CC_Xcache'''
    145 {{{
    146     VciCcXcacheWrapper(
    147         sc_module_name insname,
    148         int proc_id,
    149         const soclib::common::MappingTable &mt,
    150         const soclib::common::IntTab &initiator_index,
    151         const soclib::common::IntTab &target_index,
    152         size_t icache_ways,  // number of ways per associative set (instruction cache)
    153         size_t icache_sets,  // number of  associative sets (instruction cache)
    154         size_t icache_words,  // number of words per line (instruction cache)
    155         size_t dcache_ways,  // number of ways per associative set (data cache)
    156         size_t dcache_sets,  // number of  associative sets (data cache)
    157         size_t dcache_words);  // number of words per line (data cache)
    158 }}}
    159 '''CC_Vcache'''
    160 {{{
    161     VciCcVcacheWrapper(
    162         sc_module_name insname,
    163         int proc_id,
    164         const soclib::common::MappingTable &mt,
    165         const soclib::common::IntTab &initiator_index,
    166         const soclib::common::IntTab &target_index,
    167         size_t itlb_ways,  // number of ways per associative set (instruction TLB)
    168         size_t itlb_sets,  // number of associative sets (instruction TLB)
    169         size_t dtlb_ways,  // number of ways per associative set (data TLB)
    170         size_t dtlb_sets,  // number of associative sets (data TLB)
    171         size_t icache_ways,  // number of ways per associative set (instruction cache)
    172         size_t icache_sets,  // number of  associative sets (instruction cache)
    173         size_t icache_words,  // number of words per line (instruction cache)
    174         size_t dcache_ways,  // number of ways per associative set (data cache)
    175         size_t dcache_sets,  // number of  associative sets (data cache)
    176         size_t dcache_words);  // number of words per line (data cache)
    177 
    178122}}}
    179123