Changes between Version 34 and Version 35 of Component/Vci Xcache Wrapper


Ignore:
Timestamp:
Mar 24, 2012, 12:10:16 PM (13 years ago)
Author:
alain
Comment:

--

Legend:

Unmodified
Added
Removed
Modified

  • Component/Vci Xcache Wrapper

    v34 v35  
    66
    77These 2 hardware components are generic cache controllers, fully compliant with the
    8 VCI advanced protocol. They  can be used to interface any - single instruction issue -
     8VCI advanced protocol. They  can be used to interface a - single instruction issue -
    9932 bits RISC processor (such as Mips32, Sparc V8, Xilinx microBlaze, Altera Nios, or PPC 405) to a VCI based multi-processor system.
    1010They act directly as a wrapper for any ISS (Instruction Set Simulator) respecting the generic cache/processor interface defined in source:trunk/soclib/soclib/iss/iss2/include/iss2.h.
    … …  
    1212Each cache controller implements two separated instruction and data caches, sharing the same VCI interface.
    1313
    14  * The !VciXcacheWrapper (in short Xcache) replace the previous !VciXcache component. It has an higher simulation speed, and supports  associativity (for both the instruction and data caches).
    15  * The !VciVcacheWrapper (in short Vcache) has the same functionnalities as the Xcache, and implements a generic paged MMU.
     14The !VciVcacheWrapper component (in short Vcache) has the same functionnalities as the !VciXcacheWapper component (in short Xcache), but it implements the SoCLib generic MMU.
    1615
    1716=== General features ===
    … …  
    2423 * The number of lines must be a power of 2, and cannot be larger than 1024.
    2524 * The number of words must be a power of 2, and cannot be larger than 32.
    26  * The number of associativity levels must be a power of 2, and cannot be larger than 16.
     25 * The number of ways must be a power of 2, and cannot be larger than 16.
    2726
    2827According to the VCI advanced specification, these components use one word VCI command packets
    2928for Read bursts, and accept one word VCI response packets for Write bursts.
    30 In order to garanty the memory consistency, these cache controllers do NOT start a new VCI transaction
    31 until the previous transaction is completed. Therefore, they do NOT use the VCI PKTID and TRDID fields.
     29
     30The Xcache implements a very simple write buffer, and do NOT start a new VCI transaction
     31until the previous transaction is completed. Therefore, it doesn't use the VCI PKTID and TRDID fields.
     32
     33The Vcache controller implements a more advanced write buffer, supporting several simultaneous VCI transactions.
     34It uses the VCI TRDID field to support this functinnality.
    3235
    3336=== Instruction Cache ===
    … …  
    5861This MMU performs both the logical address to physical address translation, and access rights checking.
    5962 * The logical address is 32 bits.
    60  * The Physical address is 40 bits (or less).
    61  * It is implemented as a two level, hierarchical, page table.
    62  * Two page sizes are supported : 4 Kbytes, or 4 Mbytes.
     63 * The physical address (VCI address) is up to 40 bits.
     64 * It uses a two level, hierarchical, page table.
     65 * Two page sizes are supported : 4 Kbytes, or 2 Mbytes.
    6366 * Separated TLBs are used for instruction and data addresses.
    6467 * The TLB misses are handled by hardware (hardwired table-walk).
    … …  
    128131 * soclib::caba::!VciInitiator<vci_param> '''p_vci''' : The VCI port
    129132
    130 '''CC_Xcache''' & '''CC_Vcache'''
    131  * sc_in<bool> '''p_resetn''' : Global system reset
    132  * sc_in<bool> '''p_clk''' : Global system clock
    133  * soclib::caba::!VciInitiator<vci_param> '''p_vci_ini''' : The VCI initiator port
    134  * soclib::caba::!VciTarget<vci_param> '''p_vci_tgt''' : The VCI target port
    135 
    136133== 3) TLM-DT Implementation ==
    137134