Changes between Version 4 and Version 5 of Component/Vci Xcache Wrapper

Timestamp:

Aug 25, 2008, 1:42:13 PM (16 years ago)

Author:

alain

Comment:

--

Component/Vci Xcache Wrapper

@@ -1 +1 @@
 [wiki:Component SocLib Components General Index] 
 
-= !VciXcacheWrapper =
+= !VciXcacheWrapper /  !VciVcacheWrapper / !VciCcXcacheWrapper / !VciCcVcacheWrapper =
 
 == 1) Functional Description ==
 
-This VCI initiator is a generic cache controller, fully compliant with the 
-VCI advanced protocol. This hardware component can be used to interface any
-32 bits RISC processor (such as Mips R3000, Sparc V8, or PPC 405) to a VCI based multi-processor system.
-It acts directly as a wrapper for any ISS (Instruction Set Simulator) respecting the standardized API
+These 4 hardware components are generic cache controllers, fully compliant with the 
+VCI advanced protocol. They  can be used to interface any - single instruction issue -
+32 bits RISC processor (such as Mips R3000, Sparc V8, Xilinx microBlaze, Altera Nios, or PPC 405) to a VCI based multi-processor system.
+They act directly as a wrapper for any ISS (Instruction Set Simulator) respecting the standardized API
 defined [wiki:WritingRules/RISC here].
 
-This cache controller implements two separated instruction and data caches, sharing the same VCI interface.
+Each cache controller implements two separated instruction and data caches, sharing the same VCI interface.
 
-It provides the same functionalities as the previous !VciXcache component, with an higher simulation speed,
-an full support for associativity (for both the instruction and data caches).
 
- * The VCI ADDRESS and DATA fields must have 32 bits, and the VCI ERROR field has 1 bit.
+ * The !VciXcacheWrapper provides the same functionalities as the previous !VciXcache component. It has an higher simulation speed, and supports  associativity (for both the instruction and data caches).
+ * The !VciVcacheWrapper implement a generic paged MMU (see below).
+ * The !VciCcacheWrapper implement a directory-based cache coherence protocol (see below). 
+ * The !VciCcVcachewrapper supports both the generic MMU and the cache coherence.
+ 
+||                                        || No Virtual memory    || With Virtual Memory   ||
+||No Cache Coherence   || !VciXcacheWrapper     || !VciVcacheWrapper     ||
+||With Cache Coherence|| !VciCcXcacheWrapper || !VciCcVcacheWrapper ||
+
+=== General features ===
+
+The general characteristics are the following
+ * The VCI  DATA field must have 32 bits,
+ * The VCI  ADDRESS field must have 32 bits (when there is no MMU),
+ * The VCI ERROR field has 1 bit.
  * The number of lines must be a power of 2, and cannot be larger than 1024.
  * The number of words must be a power of 2, and cannot be larger than 32.
  * The number of associativity levels must be a power of 2, and cannot be larger than 16.
 
-In order to garanty the memory consistency, this component does NOT start a new VCI transaction
-until the previous transaction is completed. Therefore, it does not use the VCI PKTID and TRDID fields.
+According to the VCI advanced specification, these components use one word VCI command packets
+for Read MISS, and accept one word VCI response packets for Write bursts.
+In order to garanty the memory consistency, these cache controllers do NOT start a new VCI transaction
+until the previous transaction is completed. Therefore, they do NOT use the VCI PKTID and TRDID fields.
 
 === Instruction Cache ===
@@ -44 +58 @@
  * The processor is stalled in case of cached read MISS, in case of uncached read, or in case of write, if the write buffer is full.
 
-== 2) Component definition & usage ==
+=== Generic MMU ===
 
-source:trunk/soclib/soclib/module/internal_component/vci_xcache_wrapper/caba/metadata/vci_xcache_wrapper.sd
+=== Cache Coherence ===
 
-== 3) CABA  Implementation ==
+The CC_Xcache & CC_Vcache components implement a directory-based cache coherence protocol.
+The global memory directory itself should be implemented in a dedicated memory controller such as the !VciMemCache component.
+The cache coherence protocol is strongly simplified by the WRITE-THROUGH policy and is implemented by three types of packets. 
+The CC_Xcache (or CC_Vcache) component has one VCI target port, and can receive UPDATE or INVALIDATE packets, from the memory controller. When the CC-Xcache (or CC_Vcache) component discard a cache line (due to a cache line replacement following a MISS), it signals this change by a CLEANUP packet sent to the cache controller. All those ''coherence'' packets are implemented as VCI write packets to dedicated memory mapped registers.
+ * an UPDATE packet (memory controller to cache) has N+2 words : the first word contains the the line index of the modified cache line. The second word contains the index of the first modified word in the line. The N following words contain the N data values. 
+ * an INVALIDATE packet (memory controller to cache) has 1 word : it contains the line index of the modified cache line.
+ * a CLEANUP packet (cache to memory controller) has 1 word : it contains the line index of the discarded cache line.
 
+== 2) CABA  Implementation ==
+
+'''Xcache'''
+ * Usage : source:trunk/soclib/soclib/module/internal_component/vci_xcache_wrapper/caba/metadata/vci_xcache_wrapper.sd
  * interface : source:trunk/soclib/soclib/module/internal_component/vci_xcache_wrapper/caba/source/include/vci_xcache_wrapper.h
  * implementation : source:trunk/soclib/soclib/module/internal_component/vci_xcache_wrapper/caba/source/src/vci_xcache_wrapper.cpp
+'''Vcache''
+ * Usage : source:trunk/soclib/soclib/module/internal_component/vci_vcache_wrapper/caba/metadata/vci_vcache_wrapper.sd
+ * interface : source:trunk/soclib/soclib/module/internal_component/vci_vcache_wrapper/caba/source/include/vci_vcache_wrapper.h
+ * implementation : source:trunk/soclib/soclib/module/internal_component/vci_vcache_wrapper/caba/source/src/vci_vcache_wrapper.cpp
+'''CC_Vcache'''
+ * Usage : source:trunk/soclib/soclib/module/internal_component/vci_cc_xcache_wrapper/caba/metadata/vci_cc_xcache_wrapper.sd
+ * interface : source:trunk/soclib/soclib/module/internal_component/vci_xcache_wrapper/caba/source/include/vci_xcache_wrapper.h
+ * implementation : source:trunk/soclib/soclib/module/internal_component/vci_cc_xcache_wrapper/caba/source/src/vci_cc_xcache_wrapper.cpp
+'''Cc_Vcache'''
+ * Usage : source:trunk/soclib/soclib/module/internal_component/vci_cc_vcache_wrapper/caba/metadata/vci_cc_vcache_wrapper.sd
+ * interface : source:trunk/soclib/soclib/module/internal_component/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
+ * implementation : source:trunk/soclib/soclib/module/internal_component/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
 
 === CABA template parameters ===
 
-This component has two template parameters, defining respectively the width of the various VCI signals,
+All these 4 component have two template parameters, defining respectively the width of the various VCI signals,
 and the instanciated ISS.
 {{{
@@ -62 +98 @@
 
 === CABA constructor parameters ===
+'''Xcache & Vcache''' 
 {{{
-
     VciXcacheWrapper(
         sc_module_name insname, 
@@ -76 +112 @@
         size_t dcache_sets );
 }}}
-
+'''CC_Xcache & CC_Vcache''' 
+{{{
+    VciXcacheWrapper(
+        sc_module_name insname, 
+        int proc_id,
+        const soclib::common::MappingTable &mt,
+        const soclib::common::IntTab &initiator_index,
+        const soclib::common::IntTab &target_index,
+        size_t icache_lines,
+        size_t icache_words,
+        size_t icache_sets,
+        size_t dcache_lines,
+        size_t dcache_words 
+        size_t dcache_sets );
+}}}
 === CABA ports ===