wiki:Component/VciXcacheWrapper

Version 8 (modified by alain, 16 years ago) (diff)

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SocLib Components General Index

VciXcacheWrapper / VciVcacheWrapper / VciCcXcacheWrapper / VciCcVcacheWrapper

1) Functional Description

These 4 hardware components are generic cache controllers, fully compliant with the VCI advanced protocol. They can be used to interface any - single instruction issue - 32 bits RISC processor (such as Mips32, Sparc V8, Xilinx microBlaze, Altera Nios, or PPC 405) to a VCI based multi-processor system. They act directly as a wrapper for any ISS (Instruction Set Simulator) respecting the standardized API defined here.

Each cache controller implements two separated instruction and data caches, sharing the same VCI interface.

  • The VciXcacheWrapper provides the same functionalities as the previous VciXcache component. It has an higher simulation speed, and supports associativity (for both the instruction and data caches).
  • The VciVcacheWrapper implement a generic paged MMU (see below).
  • The VciCcacheWrapper implement a directory-based cache coherence protocol (see below).
  • The VciCcVcachewrapper supports both the generic MMU and the cache coherence.

No Virtual memory With Virtual Memory
No Cache Coherence VciXcacheWrapper VciVcacheWrapper
With Cache Coherence VciCcXcacheWrapper VciCcVcacheWrapper

General features

The general characteristics are the following

  • The VCI DATA field must have 32 bits,
  • The VCI ADDRESS field must have 32 bits (when there is no MMU),
  • The VCI ERROR field has 1 bit.
  • The number of lines must be a power of 2, and cannot be larger than 1024.
  • The number of words must be a power of 2, and cannot be larger than 32.
  • The number of associativity levels must be a power of 2, and cannot be larger than 16.

According to the VCI advanced specification, these components use one word VCI command packets for Read MISS, and accept one word VCI response packets for Write bursts. In order to garanty the memory consistency, these cache controllers do NOT start a new VCI transaction until the previous transaction is completed. Therefore, they do NOT use the VCI PKTID and TRDID fields.

Instruction Cache

  • It is read-only.
  • It uses the Mapping Table to support uncached segments.
  • In case of read MISS, or read uncached, the processor is stalled until the missing instruction is available.
  • The only VCI transaction generated by the Instruction cache is a read burst corresponding to a missing cache line.

Data Cache

  • The write policy is WRITE-THROUGH (the data is immediately written in memory, and the cache is updated only in case of HIT).
  • The Data cache contains a write buffer, and builds a burst when there are successive write requests in the same cache line.
  • It uses the Mapping Table to support uncached segments.
  • The Data Cache supports the following requests : Read, Write, Linked load, and Store Conditional
  • The Data cache accepts a line invalidate command.
  • Three types of VCI transactions can be generated by the data cache:
    • read burst of fixed length, corresponding to a cached read MISS,
    • one word transaction, corresponding to an uncached read, a linked load, or a store conditional.
    • write burst of variable length ( no larger than a cache line)
  • The processor is stalled in case of cached read MISS, in case of uncached read, or in case of write, if the write buffer is full.

Generic MMU

Cache Coherence

The CC_Xcache & CC_Vcache components implement a directory-based cache coherence protocol. The global memory directory itself should be implemented in a dedicated memory controller such as the VciMemCache component. The cache coherence protocol is strongly simplified by the WRITE-THROUGH policy and is implemented by three types of packets. The CC_Xcache (or CC_Vcache) component has one VCI target port, and can receive UPDATE or INVALIDATE packets, from the memory controller. When the CC-Xcache (or CC_Vcache) component discard a cache line (due to a cache line replacement following a MISS), it signals this change by a CLEANUP packet sent to the cache controller. All those coherence packets are implemented as VCI write packets to dedicated memory mapped registers.

  • an UPDATE packet (memory controller to cache) has N+2 words : the first word contains the the line index of the modified cache line. The second word contains the index of the first modified word in the line. The N following words contain the N data values.
  • an INVALIDATE packet (memory controller to cache) has 1 word : it contains the line index of the modified cache line.
  • a CLEANUP packet (cache to memory controller) has 1 word : it contains the line index of the discarded cache line.

2) CABA Implementation

Xcache

Vcache

CC_Xcache

CC_Vcache

CABA template parameters

All these 4 component have two template parameters, defining respectively the width of the various VCI signals, and the instanciated ISS. 

template<typename vci_param, typename iss_t>

CABA constructor parameters

Xcache & Vcache 

    VciXcacheWrapper(
        sc_module_name insname, 
        int proc_id,
        const soclib::common::MappingTable &mt,
        const soclib::common::IntTab &index,
        size_t icache_lines,
        size_t icache_words,
        size_t icache_sets,
        size_t dcache_lines,
        size_t dcache_words 
        size_t dcache_sets );

CC_Xcache & CC_Vcache 

    VciXcacheWrapper(
        sc_module_name insname, 
        int proc_id,
        const soclib::common::MappingTable &mt,
        const soclib::common::IntTab &initiator_index,
        const soclib::common::IntTab &target_index,
        size_t icache_lines,
        size_t icache_words,
        size_t icache_sets,
        size_t dcache_lines,
        size_t dcache_words 
        size_t dcache_sets );

CABA ports

  • sc_in<bool> p_resetn : Global system reset
  • sc_in<bool> p_clk : Global system clock
  • soclib::caba::VciInitiator<vci_param> p_vci : The VCI port

3) TLM-T Implementation

TLM-T template parameters

TLM-T constructor parameters

TLM-T ports