Changes between Version 2 and Version 3 of Component/Virtual Coprocessor Wrapper
- Timestamp:
- Jan 15, 2013, 10:01:39 AM (12 years ago)
Legend:
- Unmodified
- Added
- Removed
- Modified
-
Component/Virtual Coprocessor Wrapper
v2 v3 14 14 15 15 The task thread communicates with the ''wrapper'' with two fifo channels: 16 * the `cmd` channel, which transmits to the ''wrapper'' the SRL commands :16 * the `cmd` channel, which transmits to the ''wrapper'' the SRL commands. These commands take the form of function calls in the task code: 17 17 * `srl_mwmr_read(channel, buffer, size)` 18 18 * `srl_mwmr_write(channel, buffer, size)` … … 65 65 66 66 67 (A finir)68 69 67 = Component usage = 70 68 71 The virtual Coprocessor Wrapper is primarily intended to be used with Dsx-vm (to be released soon?), but it can also be used "by hand". In the following is an example of a dummy ''adder'' task, which makes a vectorial 32-bit addition of size 8 (i.e. there are 16 words in input and 8 words in output). 3 files must be created: 69 The virtual Coprocessor Wrapper is primarily intended to be used with Dsx-vm (to be released soon?), but it can also be used "by hand". 70 71 == Example == 72 73 In the following is an example of a dummy ''adder'' task, which makes a vectorial 32-bit addition of size 8 (i.e. there are 16 words in input and 8 words in output). 3 files must be created: 72 74 * `my_adder_copro.sd` 73 75 * `my_adder_copro.h` … … 124 126 { 125 127 126 127 public: 128 public: 128 129 ~MyAdderCopro(); 129 130 MyAdderCopro(sc_core::sc_module_name insname); 130 131 131 private: 132 133 private: 132 134 void * task_func(); // Task code 133 135 … … 155 157 156 158 tmpl(/**/)::MyAdderCopro(sc_core::sc_module_name insname) 157 159 :dsx::caba::VirtualCoprocessorWrapper(insname, stringArray("output", NULL), intArray(1, 8), stringArray("input0", "input1", NULL), intArray(2, 8, 8)) 158 160 { 159 161 } … … 173 175 out[i] = in0[i] + in1[i]; 174 176 } 177 srl_busy_cycles(2); // The computation takes 2 cycles 175 178 srl_mwmr_write(output, &out, 1); // Write 8 words to output 176 179 } … … 180 183 }}} 181 184 182 183 À compléter... 184 185 The prototype of the parent class `VirtualCoprocessorWrapper` is: 186 {{{ 187 #!cpp 188 VirtualCoprocessorWrapper( 189 sc_core::sc_module_name insname, 190 const vector<string> &fifos_out, 191 const vector<int32_t> &fifos_out_width, 192 const vector<string> &fifos_in, 193 const vector<int32_t> &fifos_in_width) 194 : soclib::caba::BaseModule(insname) 195 }}} 196 197 with 198 fifos_out:: 199 a vector containing the names of the output fifos 200 fifos_out_width:: 201 a vector containing the width of the output fifos 202 fifos_in:: 203 a vector containing the names of the input fifos 204 fifos_in_width:: 205 a vector containing the width of the input fifos 206 207 The functions `stringArray` and `intArray` construct these vectors, the first argument of intArray being the number of fifos. 208 209 210 == Component Instanciation == 211 212 === CABA Ports === 213 214 * `sc_in<bool>` '''p_resetn''' : Global system reset 215 * `sc_in<bool>` '''p_clk''' : Global system clock 216 * `FifoOutput<uint32_t> *` '''p_to_ctrl''' : list of output ports to connect to a `soclib::caba::VciMwmrControllerCas` via a `soclib::caba::FifoSignals<uint32_t>`. 217 * `FifoInput<uint32_t> *` '''p_from_ctrl''' : list of input ports to connect to a `soclib::caba::VciMwmrControllerCas` via a `soclib::caba::FifoSignals<uint32_t>`. 218 219