| 1 | [wiki:Component SocLib Components General Index] |
| 2 | |
| 3 | = !WbInterco = |
| 4 | |
| 5 | == 1) Functional Description == |
| 6 | |
| 7 | This hardware component is a generic Wishbone interconnect with a round robin arbiter. |
| 8 | |
| 9 | It is a multiplexed bus with integrated address decoding. |
| 10 | |
| 11 | == 2) Component definition & usage == |
| 12 | |
| 13 | == 3) CABA Implementation == |
| 14 | |
| 15 | === CABA sources === |
| 16 | |
| 17 | * interface : source:trunk/soclib/soclib/module/network_component/wb_interco/include/wb_interco.h |
| 18 | * implementation : source:trunk/soclib/soclib/module/network_component/wb_interco/src/wb_interco.cpp |
| 19 | * Arbiter definition:trunk/soclib/soclib/module/network_component/wb_interco/include/arbiter.h |
| 20 | * Arbiter implementation:source:trunk/soclib/soclib/module/network_component/wb_interco/src/arbiter.cpp |
| 21 | |
| 22 | === CABA Constructor parameters === |
| 23 | |
| 24 | {{{ |
| 25 | WbInterco (sc_module_name insname, |
| 26 | const soclib::common::MappingTable &mtb, |
| 27 | const size_t &nb_of_masters, |
| 28 | const size_t &nb_of_slaves |
| 29 | ) ; |
| 30 | }}} |
| 31 | |
| 32 | === CABA Ports === |
| 33 | |
| 34 | * sc_in<bool> '''p_resetn''' : Global system reset |
| 35 | * sc_in<bool> '''p_clk''' : Global system clock |
| 36 | * !WbMaster<wb_param> '''*p_to_slave''': ports to wishbone slaves |
| 37 | * !WbSlave <wb_param> '''*p_from_master''': ports from wishbone masters |
| 38 | |
| 39 | === CABA Implementation Notes === |
| 40 | |
| 41 | The !WbInterco uses the mapping table to identify the slaves and to decode addresses. The slaves must be connected to the '''p_to_slave''' ports at the position as the mapping table index. |
| 42 | |
| 43 | == 4) TLM-T implementation == |
| 44 | |
| 45 | There is no TLM-T implementation for this component. |