1 | | s |
| 1 | [wiki:Component SocLib Components General Index] |
| 2 | |
| 3 | = Processor Functional Description = |
| 4 | |
| 5 | This hardware component is a lm32 (lattice mico32) processor core. |
| 6 | |
| 7 | This ISS uses the [wiki:Component/Iss2Api ISS2 API] |
| 8 | and can be wrapped in a CABA or TLM-T [wiki:Component/VciXcacheWrapper Wrapper]. |
| 9 | * [wiki:Tools/GdbServer gdb server] support is under development. |
| 10 | |
| 11 | It implements all instructions defined in the lm32 architecture specification. |
| 12 | |
| 13 | |
| 14 | = Component definition & implementation = |
| 15 | |
| 16 | * source:trunk/soclib/soclib/iss/lm32/metadata/lm32.sd |
| 17 | * source:trunk/soclib/soclib/iss/lm32/include/lm32.h |
| 18 | * source:trunk/soclib/soclib/iss/lm32/src/lm32.cpp |
| 19 | * source:trunk/soclib/soclib/iss/lm32/src/lm32_isa.cpp |
| 20 | * source:trunk/soclib/soclib/iss/lm32/src/lm32_load_store.cpp |
| 21 | * source:trunk/soclib/soclib/iss/lm32/src/lm32_debug.cpp |
| 22 | |
| 23 | == Interrupts == |
| 24 | |
| 25 | LM32 architecture supports up to 32 external interrupt lines. This ISS implements all these interrupt lines by default. |
| 26 | |
| 27 | == Ports == |
| 28 | |
| 29 | None, it is to the wrapper to provide them. |
| 30 | |
| 31 | = Notes = |
| 32 | |
| 33 | == MMU suppurt == |
| 34 | The lm32 provided by lattice does not have an mmu. |
| 35 | |
| 36 | == Compiling programs for lm32 with SoCLib == |
| 37 | |
| 38 | Before compiling a program for the lm32 with the SoCLib framework you will need to define some system variables (usually on the ~/.soclib/soft_compilers.conf) needed to find the lm32 compiler. Below you have an example: |
| 39 | {{{ |
| 40 | sparc_CC_PREFIX = lm32-elf- |
| 41 | sparc_CFLAGS = -O2 -g -mmultiply-enabled -mdivide-enabled -msign-extend-enabled -mbarrel-shift-enabled |
| 42 | sparc_LDFLAGS = -nostdlib |
| 43 | }}} |