Changes between Version 116 and Version 117 of Component


Ignore:
Timestamp:
Mar 25, 2010, 1:26:27 PM (15 years ago)
Author:
Joel Porquet
Comment:

mainly typos

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  • Component

    v116 v117  
    11[[PageOutline()]]
    22
    3 The library contains all needed parts to create a fully working VirtualPrototype.
     3The SoCLib project is a library that contains all needed parts to create a fully working VirtualPrototype.
    44
    55Most simulation models connect around an on-chip bus.
    6 It is either a NoC or a simpler BUS or crossbar. Most
    7 SoCLib components are using the VCI on-chip-bus protocol. This
     6It can be either a NoC or a simpler BUS or a crossbar. SoCLib components are mainly using the VCI on-chip-bus protocol. This
    87makes the components easily interoperable. Moreover, VCI is simple
    98enough to ease integration of new components, without forbidding
    … …  
    1211
    1312
    14 Available models can be split up in categories
     13Available models can be split up in categories:
    1514
    1615= On-Chip-Bus/NoC implementations =
    1716
    18 Several NoC implementations exist in SoCLib, providing interconnection for most of other modules.
    19 
    2017Two main types of interconnects are available:
    21  * Virtual interconnects, implementing a typical behavior without an existing hardware equivalent.
     18 * Virtual interconnects, implementing a typical behavior but without any existing hardware equivalent.
    2219   This abstraction from an actual implementation makes simulation faster, without
    2320   making performance evaluation worse.
    24   * [wiki:Component/VciVgmn VciVgmn] acts as a typical worm-holeNoC. (M->N communication, switched network)
     21  * [wiki:Component/VciVgmn VciVgmn] acts as a typical worm-hole NoC. (M->N communication, switched network)
    2522  * [wiki:Component/VciVgsb VciVgsb] acts as a classical BUS. (1 at-a-time communication, synchronous response)
    26  * Actual interconnects, which can be implemented as RTL
     23 * Actual interconnects, which can be implemented in RTL
    2724  * BUSes
    2825   * [wiki:Component/VciPiBus VciPibus] : A VCI compliant PIBUS implementation.
    … …  
    3229  * 2D-meshes:
    3330   * [wiki:Component/VciDspin VciDspin] : A VCI compliant DSPIN micro-network.
    34    * [wiki:Component/VirtualDspinNetwork VirtualDspinNetwork] : A VCI compliant Dspin micro-network with virtual channels.
     31   * [wiki:Component/VirtualDspinNetwork VirtualDspinNetwork] : A VCI compliant DSPIN micro-network with virtual channels.
    3532   * [wiki:Component/VciAnoc VciAnoc] : A VCI compliant ANOC micro-network.
    3633  * Ring-based:
    3734   * [wiki:Component/VciSimpleRingNetwork VciSimpleRingNetwork] : A VCI compliant ring interconnect.
    38    * [wiki:Component/VciLocalRingNetwork  VciLocalRingNetwork]  : A VCI compliant ring interconnect.
     35   * [wiki:Component/VciLocalRingNetwork  VciLocalRingNetwork]  : A VCI compliant ring interconnect. (targeting local interconnection, in a clusterized architecture)
    3936
    4037== On-Chip-Bus/NoC Protocol adapters ==
    … …  
    5653SoCLib provides different caches, with different features.
    5754All caches can be used with all ISSes, some features
    58 may just be unavailable in certain configurations (eg. not all CPU support MMU-aware caches).
     55may just be unavailable in certain configurations (e.g. not all CPU support MMU-aware caches).
    5956
    6057Cache models:
    … …  
    6865  * [wiki:Component/Arm Arm], with ARM-v6 instruction set (ARM11, Cortex-M0, Cortex-M1)
    6966  * [wiki:Component/Sparcv8 Sparc v8]
    70   * [wiki:Component/lm32 Lattice Mico 32]
     67  * [wiki:Component/lm32 Lattice Micro 32]
    7168  * [wiki:Component/NIOSII NiosII]
    7269  * [wiki:Component/IssIss2 IssIss2] : This wrapper may be necessary to use
    … …  
    8077ISS instrumenting tools:
    8178  * [wiki:Tools/GdbServer] : A GDB-server wrapper, for any ISS.
    82   * [wiki:Tools/MemoryChecker] : A wrapper providing walgrind-like features, for any ISS.
     79  * [wiki:Tools/MemoryChecker] : A wrapper providing valgrind-like features, for any ISS.
    8380
    8481= Memories =
    … …  
    110107 * [wiki:Component/VciMultiTimer VciTimer] : A memory mapped timer controller
    111108 * [wiki:Component/VciIcu VciIcu] : A memory mapped interrupt controller
    112  * [wiki:Component/Mailbox Mailbox] : A mailbox component allows several processors to communicate via an interrupt mecanism
     109 * [wiki:Component/Mailbox Mailbox] : A mailbox component allows several processors to communicate via an interrupt mechanism
    113110
    114111 * [wiki:Component/VciXicu VciXicu] : A memory mapped Hardware interrupt + Timer + IPI controller (all the 3 above controllers in 1)