Changes between Version 121 and Version 122 of Component


Ignore:
Timestamp:
Mar 30, 2010, 3:24:47 AM (15 years ago)
Author:
Nicolas Pouillon
Comment:

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  • Component

    v121 v122  
    3535   * [wiki:Component/VciLocalRingNetwork  VciLocalRingNetwork]  : A VCI compliant ring interconnect. (targeting local interconnection, in a clusterized architecture)
    3636
    37 == On-Chip-Bus/NoC Protocol adapters ==
     37== OCB/NoC Protocol adapters ==
    3838
    3939 * [wiki:Component/VciPCI VciPCI] : A bridge to the PCI bus
    … …  
    4545= Processor + cache =
    4646
    47 In SoCLib, processor+cache bundles are designed as two distinct entities. This has several advantages:
     47In SoCLib, processor+cache bundles are designed [PapersAndPublications#ISSdesign as two distinct entities]. This has several advantages:
    4848 * Many CPU cores out there are just the same instruction set with variations on the implementation (pipeline stages, cache, coherency, coprocessors, …)
    4949 * Modeling a cache alone is easier