[[PageOutline()]] The SoCLib project is a library that contains all needed parts to create a fully working VirtualPrototype. Most simulation models connect around an on-chip bus. It can be either a NoC or a simpler BUS or a crossbar. SoCLib components are mainly using the VCI on-chip-bus protocol. This makes the components easily interoperable. Moreover, [VciProtocol VCI] is simple enough to ease integration of new components, without forbidding translation of VCI to other protocols. See [#On-Chip-BusNoCProtocoladapters On-Chip-Bus/NoC Protocol adapters]. Available models can be split up in categories: = On-Chip-Bus/NoC implementations = Two main types of interconnects are available: * Virtual interconnects, implementing a typical behavior but without any existing hardware equivalent. This abstraction from an actual implementation makes simulation faster, without making performance evaluation worse. * [wiki:Component/VciVgmn VciVgmn] acts as a typical worm-hole NoC. (M->N communication, switched network) * [wiki:Component/VciVgsb VciVgsb] acts as a classical BUS. (1 at-a-time communication, synchronous response) * Physical interconnects, for which it exists a synthesisable RTL model. * BUSes * [wiki:Component/VciPiBus VciPibus] : A VCI compliant PIBUS implementation. * [wiki:Component/VciAvalonBus VciAvalonBus] : A VCI compliant AVALON bus interconnect. * [wiki:Component/WbInterco WbInterco] : A Wishbone compliant bus interconnect. * Crossbars: * [wiki:Component/VciLocalCrossbar VciLocalCrossbar] : A VCI compliant crossbar. * 2D-meshes: * [wiki:Component/VciDspin VciDspin] : A VCI compliant DSPIN micro-network. * [wiki:Component/VirtualDspinNetwork VirtualDspinNetwork] : A VCI compliant DSPIN micro-network with virtual channels. * [wiki:Component/VciAnoc VciAnoc] : A VCI compliant ANOC micro-network. * Ring-based: * [wiki:Component/VciSimpleRingFast VciSimpleRingFast] : A VCI compliant ring interconnect. * [wiki:Component/VciLocalRingFast VciLocalRingFast] : A VCI compliant ring interconnect. (targeting local interconnection, in a clusterized architecture) == OCB/NoC Protocol adapters == * [wiki:Component/VciPCI VciPCI] : A bridge to the PCI bus == OCB/NoC configuration utilities == * [wiki:Component/MappingTable MappingTable] : A tool to declare and list all memory segments used in a platform and to define the memory mapping. = Processor + cache = In SoCLib, processor+cache bundles are designed [PapersAndPublications#ISSdesign as two distinct entities]. This has several advantages: * Many CPU cores out there are just the same instruction set with variations on the implementation (pipeline stages, cache, coherency, coprocessors, …) * Modeling a cache alone is easier * Modeling an ISS alone is easier * Instrumentation tools can be factored-out (gdb, profiling, …) SoCLib provides different caches, with different features. All caches can be used with all ISSes, some features may just be unavailable in certain configurations (e.g. not all CPU support MMU-aware caches). Cache models: * [wiki:Component/VciXcacheWrapper VciXcacheWrapper] : A generic, VCI compliant, cache controller for Iss2Api processors * [wiki:Component/VciXcacheWrapper VciVcacheWrapper] : A generic, VCI compliant, cache controller for Iss2Api processors supporting virtual memory mapping ISS models using [wiki:Component/Iss2Api the Iss2API] * [wiki:Component/Mips32 Mips32], Mips32-!r1 with FPU model * [wiki:Component/Ppc405 Ppc405] * [wiki:Component/Arm Arm], with ARM-v6t instruction set (ARM11, Cortex-M0, Cortex-M1) * [wiki:Component/Sparcv8 Sparc v8], with optional FPU * [wiki:Component/lm32 Lattice Mico 32] * [wiki:Component/NIOSII NiosII] * [wiki:Component/IssIss2 IssIss2] : This wrapper may be necessary to use the following [wiki:Component/IssApi IssApi]-compliant ISSes (!IssApi is deprecated. New ISSes should implement the Iss2Api) * [wiki:Component/MicroBlaze MicroBlaze] * [wiki:Component/ST231 ST231] * [wiki:Component/TMS320C62 TMS320C62] ISS instrumenting tools: * [wiki:Tools/GdbServer] : A GDB-server wrapper, for any ISS. * [wiki:Tools/MemoryChecker] : A wrapper providing valgrind-like features, for any ISS. = Memories = * [wiki:Component/VciSimpleRom VciSimpleRom] : A multi-segment embedded ROM controller * [wiki:Component/VciHeterogeneousRom VciHeterogeneousRom] : A multi-segment embedded ROM controller, with differentiated answers depending on initiator * [wiki:Component/VciMultiRam VciRam] : A multi-segment embedded RAM controller * [wiki:Component/VciSimpleRam VciSimpleRam] : A multi-segment embedded RAM controller with parameterized latency Memory loading is done through [wiki:Component/Loader Loader] : A binary-file loader (ELF, COFF, plain) = IO Controllers = Character devices: * [wiki:Component/VciMultiTty VciMultiTty] : A memory mapped multi-TTY controller * [wiki:Component/VciLogConsole VciLogConsole] : A memory-mapped text log sink, for debugging purposes * [wiki:Component/VciI2cInterface VciI2cInterface] : An I2C bus controller. Block devices (with DMA): * [wiki:Component/VciFdAccess VciFdAccess] : A file system access controller * [wiki:Component/VciBlockDevice VciBlockDevice] : A single channel block device controller * [wiki:Component/VciMultiAhci VciMultiAhci] : A multi-channel block device controller respecting the AHCI standard * [wiki:Component/VciAhciSdc VciAhciSdc] : A SD card controller respecting the AHCI standard Ethernet Network Controllers: * [wiki:Component/VciMasterNic VciMasterNic] : A Gigabit Ethernet network controller, with DMA capability. * [wiki:Component/VciEthernet VciEthernet] : An ethernet network controller with host tap support. * [wiki:Component/VciMultiNic VciMultiNic] : A multi-channels Gigabit Ethernet network controller. Graphic Controllers: * [wiki:Component/VciFrameBuffer VciFrameBuffer] : A frame buffer for YUV or RVB image display. = Internal controllers = * [wiki:Component/VciMultiTimer VciTimer] : A memory mapped timer controller * [wiki:Component/VciRtTimer VciRtTimer] : A memory mapped deadlines based timer controller (similar to intel HPET) * [wiki:Component/VciLocks VciLocks] : A memory mapped locks controller (memory with implicit test-and-set) * [wiki:Component/Mailbox Mailbox] : A mailbox component allows several processors to communicate via an interrupt mechanism * [wiki:Component/VciIcu VciIcu] : A single-channel memory mapped interrupt controller * [wiki:Component/VciMultiIcu VciMultiIcu] : A multi-channels memory mapped interrupt controller * [wiki:Component/VciXicu VciXicu] : A multi-channels (Hardware interrupt + Timer + Software interrupt) controller * [wiki:Component/VciIopic VciIopic] : A programmable Hardware Interrupt to Software Interrupt translator * [wiki:Component/VciDma VciDma] : A single channel DMA engine * [wiki:Component/VciMultiDma VciMultiDma] : A multi channels DMA engine * [wiki:Component/VciChbufDma VciChbufDma] : A multi channels Chained Buffers DMA engine * [wiki:Component/VciMwmrDma VciMwmrDma] : A generic DMA controller for hardware coprocessors * [wiki:Component/VciMwmrController VciMwmrController] : A Mwmr channels controller * [wiki:Component/VciMwmrControllerLf VciMwmrControllerLf] : Another Mwmr channels controller, with a lock-free software protocol = Dedicated coprocessors, not necessarily connected to On-Chip-Bus = * [wiki:Component/Tc4200 Tc4200] : A WiMAX LDPC decoder * [wiki:Component/Tc4200_enc Tc4200_enc] : a WiMAX LDPC encoder * [wiki:Component/trx_ofdm trx_ofdm] : A FFT and IFFT coprocessor * [wiki:Component/FIR128 FIR128] : A 128-taps Finite Impulse Response filter * [wiki:Component/Upsampling Upsampling] : An interpolation component * [wiki:Component/Downsampling Downsampling] : A decimation component * [wiki:Component/Synchronization Synchronization] : A synchronization component * [wiki:Component/Mapping Mapping] : A mapping component * [wiki:Component/Demapping Demapping] : A demapping component * [wiki:Component/FHT FHT] : A Fast Hartley Transform component * [wiki:Component/Tc1700 Tc1700] : A triple mode turbo decoder (3GPP-LTE, HSPA, WiMAX) = Debugging tools = == Simulation controller utilities == * [wiki:Component/VciSimHelper VciSimHelper] : A memory-mapped simulation control tool, can call `sc_stop` or `exit` upon specific memory access == VCI debugging == * [wiki:Component/VciLogger VciLogger] : A VCI spy, useful for debugging network messages = Simulation MoC wrappers = Some components are just syntactical wrappers in order to mix CABA and TLM-DT simulation models: * [wiki:Component/VciInitiatorTransactor VciInitiatorTransactor] : A VCI CABA Initiator compliant VCI TLM-DT Initiator. * [wiki:Component/VciTargetTransactor VciTargetTransactor] : A VCI CABA Target compliant VCI TLM-DT Target. = Component factored-out code library = These are common parts of modules that have been factored-out to ease current and future components writing. Their usage is not mandatory for newly-written components, but is useful. * [wiki:Component/VciTargetFsm VciTargetFsm] : A generic CABA submodule for handling the VCI fsm part of a target components, so that you can focus on the functionality * [wiki:Component/TtyWrapper TtyWrapper] : A simulator-side TTY abstraction tool, used by the [wiki:Component/VciMultiTty VciMultiTty] component * [wiki:Component/ProcessWrapper ProcessWrapper] : A simulator-side fork/exec abstraction tool, with process' stdin/stdout communication * [wiki:Component/FbController FbController] : A simulator-side framebuffer abstraction tool