= Processor ISS (Instruction Set Simulator) =

These ISS must be wrapped in a CABA, TLM, or TLMDT wrapper to be used in a SoCLib platforms.
Example of such a wrapper is the [wiki:Component/VciXcacheWrapper VciXcacheWrapper] component. 

 * [wiki:Component/Iss2Api processors using the Iss2API]
  * [wiki:Component/Mips32 Mips32]
  * [wiki:Component/Ppc405 Ppc405]
  * [wiki:Component/Arm Arm], with ARM-v6 instruction set (ARM11, Cortex-M0, Cortex-M1)
  * [wiki:Component/Sparcv8 Sparc v8]
  * [wiki:Component/lm32 Lattice Mico 32]
  * [wiki:Component/NIOSII NiosII]

 * [wiki:Component/IssApi processors using the IssAPI]
  * [wiki:Component/MicroBlaze MicroBlaze]
  * [wiki:Component/ARM7TDMI ARM7TDMI]
  * [wiki:Component/ARM966 ARM966]
  * [wiki:Component/ST231 ST231]
  * [wiki:Component/TMS320C62 TMS320C62]
  * [wiki:Component/MPC7447A MPC7447A]

  * [wiki:Tools/GdbServer] : A GDB-server wrapper, for any ISS using the Iss2API.
  * [wiki:Component/IssIss2 IssIss2] : Utility wrapper to use any [wiki:Component/IssApi IssApi] compliant ISS in an [wiki:Component/Iss2Api Iss2Api] [#IssWrapperscaches wrapper]

= Components =

== VCI Targets ==
 
 * [wiki:Component/VciMultiRam VciRam] : A multi-segment embedded Ram controller
 * [wiki:Component/VciSimpleRam VciSimpleRam] : A multi-segment embedded Ram controller with parameterized latency
 * [wiki:Component/VciMultiTty VciMultiTty] : A memory mapped multi-TTY controller 
 * [wiki:Component/VciXicu VciXicu] : A memory mapped Hardware interrupt + Timer + IPI controller 
 * [wiki:Component/VciMultiTimer VciTimer] : A memory mapped timer controller 
 * [wiki:Component/VciIcu VciIcu] : A memory mapped interrupt controller 
 * [wiki:Component/VciLocks VciLocks] : A memory mapped locks controller
 * [wiki:Component/VciPCI VciPCI] : A bridge to the PCI bus
 * [wiki:Component/VciLogConsole VciLogConsole] : A memory-mapped text log sink
 * [wiki:Component/VciSimHelper VciSimHelper] : A memory-mapped simulation control tool
 * [wiki:Component/Mailbox Mailbox] : A mailbox component allows several processors to communicate via an interrupt mecanism
 * [wiki:Component/VciFrameBuffer VciFrameBuffer] : A frame buffer for YUV or RVB image display.
 * [wiki:Component/VciI2cInterface VciI2cInterface] : An I2C bus controller.

== VCI Initiators ==

 * Iss Wrappers (caches)
  * [wiki:Component/VciXcacheWrapper VciXcacheWrapper] : A generic, VCI compliant, cache controller for [#ProcessorISSInstructionSetSimulator Iss2Api] processors
  * [wiki:Component/VciXcacheWrapper VciVcacheWrapper] : A generic, VCI compliant, cache controller for [#ProcessorISSInstructionSetSimulator Iss2Api] processors supporting virtual memory
 * Other initiators
  * [wiki:Component/VciXcache VciXcache] : A cache controller for 32 bits [#ProcessorISSInstructionSetSimulator IssApi] processors (deprecated)
  * [wiki:Component/VciDma VciDma] : A DMA engine
  * [wiki:Component/VciFdAccess VciFdAccess] : A file system access controller
  * [wiki:Component/VciBlockDevice VciBlockDevice] : A block device controller
  * [wiki:Component/VciMwmrController VciMwmrController] : A Mwmr channels controller
  * [wiki:Component/VciMwmrControllerLf VciMwmrControllerLf] : Another Mwmr channels controller

== VCI Interconnects ==

 * [wiki:Component/VciVgmn VciVgmn] : A VCI compliant generic micro-network. 
 * [wiki:Component/VciVgsb VciVgsb] : A VCI compliant generic system bus.
 * [wiki:Component/VciLocalCrossbar VciLocalCrossbar] : A VCI compliant crossbar.
 * [wiki:Component/VciPiBus VciPibus] : A VCI compliant PIBUS implementation.
 * [wiki:Component/VciDspin VciDspin] : A VCI compliant DSPIN micro-network.
 * [wiki:Component/VciSimpleRingNetwork VciSimpleRingNetwork] : A VCI compliant ring interconnect.
 * [wiki:Component/VciLocalRingNetwork  VciLocalRingNetwork]  : A VCI compliant ring interconnect.
 * [wiki:Component/VciAvalonBus  VciAvalonBus]  : A VCI compliant AVALON bus interconnect.
 * [wiki:Component/VciAnoc VciAnoc] : A VCI compliant ANOC micro-network.
 * [wiki:Component/VirtualDspinNetwork VirtualDspinNetwork] : A VCI compliant Dspin micro-network with virtual channels.
 * [wiki:Component/VciInitiatorTransactor VciInitiatorTransactor] : A VCI CABA Initiator compliant VCI TLM-DT Initiator.
 * [wiki:Component/VciTargetTransactor VciTargetTransactor] : A VCI CABA Target compliant VCI TLM-DT Target.

== VCI Utilities ==

 * [wiki:Component/VciLogger VciLogger] : A VCI spy, useful for debugging network messages

= Dedicated coprocessors =

  * [wiki:Component/Tc4200 Tc4200] : A WiMAX LDPC decoder
  * [wiki:Component/Tc4200_enc Tc4200_enc] : a WiMAX LDPC encoder
  * [wiki:Component/trx_ofdm trx_ofdm] : A FFT and IFFT coprocessor
  * [wiki:Component/FIR128 FIR128] : A 128-taps Finite Impulse Response filter
  * [wiki:Component/Upsampling Upsampling] : An interpolation component
  * [wiki:Component/Downsampling Downsampling] : A decimation component
  * [wiki:Component/Synchronization Synchronization] : A synchronization component
  * [wiki:Component/Mapping Mapping] : A mapping component
  * [wiki:Component/Demapping Demapping] : A demapping component
  * [wiki:Component/FHT FHT] : A Fast Hartley Transform component
  * [wiki:Component/Tc1700 Tc1700] : A triple mode turbo decoder (3GPP-LTE, HSPA, WiMAX)

= Common utilities =

 * [wiki:Component/MappingTable MappingTable] : A tool to declare and list all memory segments used in a platform and to define the memory mapping.
 * [wiki:Component/Loader Loader] : A binary-file loader (ELF, COFF, plain)
 * [wiki:Component/VciTargetFsm VciTargetFsm] : A generic CABA submodule for handling the VCI fsm part of a target components, so that you can focus on the functionality
 * [wiki:Component/TtyWrapper TtyWrapper] : A simulator-side TTY abstraction tool, used by the [wiki:Component/VciMultiTty VciMultiTty] component
 * [wiki:Component/ProcessWrapper ProcessWrapper] : A simulator-side fork/exec abstraction tool, with process' stdin/stdout communication
 * [wiki:Component/FbController FbController] : A simulator-side framebuffer abstraction tool