= SoCLib Components General Index =

== VCI Targets ==
 
 * [wiki:Component/VciMultiRam VciMultiRam] : A multi-segment embedded Ram controller 
 * [wiki:Component/VciMultiTty VciMultiTty] : A memory mapped multi-TTY controller 
 * [wiki:Component/VciMultiTimer VciMultiTimer] : A memory mapped multi-Timer controller 
 * [wiki:Component/VciIcu VciIcu] : A memory mapped interrupt controler 
 * [wiki:Component/VciLocks VciLocks] : A memory mapped locks controller

== VCI Initiators ==

 * [wiki:Component/VciXcache VciXcache] : A generic data & instruction cache controller for RISC processors

== Processors ==

 * [wiki:Component/Mips Mips] : A Mips R3000 processor core

== Dedicated coprocessors ==

== VCI Interconnects ==

 * [wiki:Component/VciVgmn VciVgmn] : A VCI advanced generic micro-network 
 * [wiki:Component/VciPiInitiatorWrapper VciPiInitiatorWrapper] : A VCI-PIBUS protocol converter for a VCI initiator
 * [wiki:Component/VciPiTargetWrapper VciPiTargetWrapper] : A VCI-PIBUS protocol converter for a VCI target 
 * [wiki:Component/PibusBcu PibusBcu] : A PIBUS controller 

= Common utilities =

 * [wiki:Component/TtyWrapper TtyWrapper] : A simulator-side TTY abstraction tool, used by [wiki:Component/VciMultiTty VciMultiTty]