= SoCLib components documentation =

== VCI Targets ==
 
 * [wiki:Component/VciMultiRam VciRam] : A multi-segment embedded Ram controller 
 * [wiki:Component/VciMultiTty VciMultiTty] : A memory mapped multi-TTY controller 
 * [wiki:Component/VciMultiTimer VciMultiTimer] : A memory mapped multi-Timer controller 
 * [wiki:Component/VciIcu VciIcu] : A memory mapped interrupt controller 
 * [wiki:Component/VciLocks VciLocks] : A memory mapped locks controller

== VCI Initiators ==

 * [wiki:Component/VciXcache VciXcache] : A generic data & instruction cache controller for 32 bits RISC processors
 * [wiki:Component/VciDma VciDma] : A DMA engine
 * [wiki:Component/VciFdAccess VciFdAccess] : A component wrapping access to simulator file descriptors
 * [wiki:Component/VciMwmrController VciMwmrController] : A component allowing access to Mwmr channels

== VCI Interconnects ==

 * [wiki:Component/VciVgmn VciVgmn] : A VCI advanced generic micro-network 
 * [wiki:Component/VciLocalCrossbar VciLocalCrossbar] : A VCI crossbar with a dedicated port to access the global micro-network
 * [wiki:Component/VciPiInitiatorWrapper VciPiInitiatorWrapper] : A VCI-PIBUS protocol converter for a VCI initiator
 * [wiki:Component/VciPiTargetWrapper VciPiTargetWrapper] : A VCI-PIBUS protocol converter for a VCI target 
 * [wiki:Component/PibusBcu PibusBcu] : A PIBUS controller 
 * [wiki:Component/VciRingInitiatorWrapper VciRingInitiatorWrapper] : A VCI-Ring controler for a VCI initiator
 * [wiki:Component/VciRingTargetWrapper VciRingTargetWrapper] : A VCI-Ring controler for a VCI target
 * [wiki:Component/RingRegister RingRegister] : A pipe-line stage for a Ring interconnect
 * [wiki:Component/VciDspinInitiatorWrapper VciDspinInitiatorWrapper] : A VCI-DSPIN protocol converter for a VCI initiator
 * [wiki:Component/VciDspinTargetWrapper VciDspinTargetWrapper] : A VCI-DSPIN protocol converter for a VCI target 
 * [wiki:Component/DspinRouter DspinRouter] : The DSPIN router  

= Processor wrappers =

 * [wiki:Component/IssWrapper IssWrapper] : A generic ISS wrapper, used to build CABA models for 32 bits RISC processors

= Common utilities =

 * [wiki:Component/TtyWrapper TtyWrapper] : A simulator-side TTY abstraction tool, used by [wiki:Component/VciMultiTty VciMultiTty]
 * [wiki:Component/MappingTable MappingTable] : A tool to declare and list all memory segments in a platform

= Instruction Set Simulators =

 * [wiki:Component/Mips Mips] : Mips-R3000
 * [wiki:Component/Ppc405 Ppc405] : PPC405
 * [wiki:Component/MicroBlaze MicroBlaze] : !MicroBlaze
 * [wiki:Component/NIOSII NiosII] : NiosII