| 5 | | ''A Generic Instruction Set Simulator API for Timed and Untimed Simulation and Debug of MP2-SoCs'' |
| 6 | | At RSP'09, doi [http://dx.doi.org/10.1109/RSP.2009.11 10.1109/RSP.2009.11] |
| | 13 | * Nicolas Pouillon, Alexandre Becoulet, Aline Vieira-de-Mello, François Pêcheux, Alain Greiner[[BR]] |
| | 14 | ''A Generic Instruction Set Simulator API for Timed and Untimed Simulation and Debug of MP2-!SoCs''[[BR]] |
| | 15 | At [http://www.rsp-symposium.org/ RSP'09], doi [http://dx.doi.org/10.1109/RSP.2009.11 10.1109/RSP.2009.11] |
| 8 | | This paper presents a method for designing SystemC-compliantInstruction Set Simulators (ISS) that address three of the majorproblems system designers are faced with when modeling MP-!SoCs architectures: the multiple levels of abstraction of the simulation models supporting the design space exploration, the simulation speed,and the debug of the multithreaded embedded application. First, this paper presents the ISS API and principles; then it describes howthe same ISS can support SystemC simulation at several abstraction levels: untimed transaction level, approximately timed transactionlevel, and cycle accurate; then, it describes how the proposed ISS API has been used by six different laboratories - in the framework of theSoCLib project - to share the same L1 cache simulation model, and towrap seven different processor cores in the same generic wrappers. Finally we demonstrate how the proposed API has been exploited to develop a generic debug and instrumentation infrastructure that can be used for all the processor cores, and allthe abstraction levels supported by the SoCLib virtual prototyping platform. |
| | 17 | == Fast CABA simulation == |
| | 18 | |
| | 19 | * Richard Buchmann, Alain Greiner[[BR]] |
| | 20 | ''A Fully Static Scheduling Approach for Fast Cycle Accurate SystemC Simulation of MPSoCs''[[BR]] |
| | 21 | At [http://www.ieee-icm.com/2007/ ICM'07], doi: [http://dx.doi.org/10.1109/ICM.2007.4497671 10.1109/ICM.2007.4497671] |
| | 22 | |
| | 23 | = About studies evaluating modeling of hardware components = |
| | 24 | |
| | 25 | == NoC == |
| | 26 | |
| | 27 | * Alain Greiner, Sami Taktak, Zhen Zhang[[BR]] |
| | 28 | ''A Reconfigurable Routing Algorithm for a Fault-Tolerant 2D-Mesh Network-on-Chip''[[BR]] |
| | 29 | At [http://www2.dac.com/45th+dac+_2008_.aspx DAC'08], doi: [http://dx.doi.org/10.1145/1391469.1391584 10.1145/1391469.1391584] |
| | 30 | |
| | 31 | = Using SoCLib as virtual prototype = |
| | 32 | |
| | 33 | == MWMR == |
| | 34 | |
| | 35 | * Alain Greiner, Etienne Faure, Nicolas Pouillon, Daniela Genius[[BR]] |
| | 36 | ''A Generic Hardware / Software Communication Middleware for Streaming Applications on Shared Memory Multi Processor Systems-on-Chip''[[BR]] |
| | 37 | At [http://www.ecsi-association.org/ecsi/fdl/fdl09/mainpage.asp FDL'09], [http://www-asim.lip6.fr/pub/reports/2009/ar.grein.fdl.1.2009.pdf PDF] |
| | 38 | |
| | 39 | * Daniela Genius, Etienne Faure, Nicolas Pouillon[[BR]] |
| | 40 | ''Deploying a Telecommunication Application on Multiprocessor Systems-on-Chip''[[BR]] |
| | 41 | At [http://www.ecsi-association.org/ecsi/dasip/dasip07/main.asp?fn=def DASIP'07], [http://www-soc.lip6.fr/~genius/dasip.pdf PDF] |
| | 42 | |
| | 43 | == Packet networks == |
| | 44 | |
| | 45 | * Daniela Genius, Alix Munier Kordon, Khouloud Zine el Abidine[[BR]] |
| | 46 | ''A Buffer Space Optimal Solution for Re-establishing the Packet Order in a MPSoC Network Processor''[[BR]] |
| | 47 | At Europar'09 doi: [http://dx.doi.org/10.1007/978-3-642-03869-3_23 10.1007/978-3-642-03869-3_23] |
