[[PageOutline]] = About SoCLib design = == TLM-DT == * Aline Vieira-de-Mello, Isaac Maia, Alain Greiner, François Pêcheux[[BR]] ''Parallel Simulation of SystemC TLM 2.0 Compliant MPSoC on SMP Workstations''[[BR]] At [http://www.date-conference.com/ Date'10] * Emmanuel Viaud, François Pêcheux and Alain Greiner.[[BR]] ''An efficient TLM/T modeling and simulation environment based on conservative parallel discrete event principles'',[[BR]] In Proceedings of the conference on Design, automation and test in Europe, 2006, pp 94-99. == ISS design == * Nicolas Pouillon, Alexandre Becoulet, Aline Vieira-de-Mello, François Pêcheux, Alain Greiner[[BR]] ''A Generic Instruction Set Simulator API for Timed and Untimed Simulation and Debug of MP2-!SoCs''[[BR]] At [http://www.rsp-symposium.org/ RSP'09], doi [http://dx.doi.org/10.1109/RSP.2009.11 10.1109/RSP.2009.11] [attachment:rsp_09_iss2.pdf slides] == Fast CABA simulation == * Marius Gligor, Frédéric Pétrot[[BR]] ''Handling dynamic frequency changes in statically scheduled cycle-accurate simulation''[[BR]] ASP-DAC 2011, pp 407-412, Yokohama, Japan. * Richard Buchmann, Alain Greiner[[BR]] ''A Fully Static Scheduling Approach for Fast Cycle Accurate SystemC Simulation of MPSoCs''[[BR]] At [http://www.ieee-icm.com/2007/ ICM'07], doi: [http://dx.doi.org/10.1109/ICM.2007.4497671 10.1109/ICM.2007.4497671] * Richard Buchmann, Alain Greiner, Frédéric Pétrot.[[BR]] ''Fast Cycle Accurate Simulation To Simulate Event-Driven Behavior''.[[BR]] In International Conference on Electronic, Circuits and Systems, Cairo, Egypt, September 2004, pp. 37-40. = About studies evaluating modeling of hardware components = == NoC == * Alain Greiner, Sami Taktak, Zhen Zhang[[BR]] ''A Reconfigurable Routing Algorithm for a Fault-Tolerant 2D-Mesh Network-on-Chip''[[BR]] At [http://www2.dac.com/45th+dac+_2008_.aspx DAC'08], doi: [http://dx.doi.org/10.1145/1391469.1391584 10.1145/1391469.1391584] == Caches == * Pierre Guironnet de Massas and Fréderic Pétrot.[[BR]] ''Evaluation of the implementation cost of cache coherence protocols using omniscient actions'',[[BR]] In Design Automation for Embedded Systems, Vol. 14, n° 1, Springer, pp 21-42, mars 2010. * Pierre Guironnet de Massas and Frédéric Pétrot.[[BR]] ''Comparison of memory write policies for NoC based multicore cache coherent systems''.[[BR]] In Design Automation and Test in Europe, Munchen, Germany, Mar 2008. IEEE, pp. 997–1002. * Frédéric Pétrot, Alain Greiner, Pascal Gomez.[[BR]] ''On cache coherency and memory consistency issues in NoC based shared memory multiprocessor SoC architectures''.[[BR]] In 9th EUROMICRO Conference on Digital System Design, Dubrovnik, Croatia, August 2006, pp. 53-60. == Transactional Memories == * Quentin Meunier and Frédéric Pétrot.[[BR]] ''Lightweight Transactional Memory Systems for NoCs Based Architectures : Design, Implementation and Comparison of Two Policies''.[[BR]] In Journal of Parallel and Distributed Computing, Elsevier, accepted for publication, february 2010. * Quentin Meunier and Frédéric Pétrot.[[BR]] ''Lightweight Transactional Memory Systems for Large Scale Shared Memory MPSoCs''.[[BR]] In 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, Toulouse, France, june 2009. IEEE, pp 432-435. = Using SoCLib as virtual prototyping platform = == Middlewares == * Alain Greiner, Etienne Faure, Nicolas Pouillon, Daniela Genius[[BR]] ''A Generic Hardware / Software Communication Middleware for Streaming Applications on Shared Memory Multi Processor Systems-on-Chip''[[BR]] At [http://www.ecsi-association.org/ecsi/fdl/fdl09/mainpage.asp FDL'09], [http://www-asim.lip6.fr/pub/reports/2009/ar.grein.fdl.1.2009.pdf PDF] * Daniela Genius, Etienne Faure, Nicolas Pouillon[[BR]] ''Deploying a Telecommunication Application on Multiprocessor Systems-on-Chip''[[BR]] At [http://www.ecsi-association.org/ecsi/dasip/dasip07/main.asp?fn=def DASIP'07], [http://www-soc.lip6.fr/~genius/dasip.pdf PDF] * Quentin L. Meunier, Frédéric Pétrot, Jean-Louis Roch[[BR]] ''Hardware/software support for adaptive work-stealing in on-chip multiprocessor''[[BR]] in Journal of Systems Architecture - Embedded Systems Design 56(8): 392-406 (2010) == Packet networks == * Daniela Genius, Alix Munier Kordon, Khouloud Zine el Abidine[[BR]] ''A Buffer Space Optimal Solution for Re-establishing the Packet Order in a MPSoC Network Processor''[[BR]] At Europar'09 doi: [http://dx.doi.org/10.1007/978-3-642-03869-3_23 10.1007/978-3-642-03869-3_23] == Operating Systems (Mutek - DNA/OS) == * Marius Gligor, Nicolas Fournel, Frédéric Pétrot.[[BR]] ''Adaptive Dynamic Voltage and Frequency Scaling Algorithm for Symmetric Multiprocessor Architecture''.[[BR]] In Proceedings of the Euromicro Conference on Digital System Design, pages 613–616, Patras, Greece, aug. 2009. * Xavier Guérin and Frédéric Pétrot.[[BR]] ''A System Framework for the Design of Embedded Software Targeting Heterogeneous Multi-Core SoCs''.[[BR]] In Proceedings of the Application-specific Systems, Architectures and Processors conference, pages 153–160, Boston, MA, jul. 2009 (got a best paper award). == Applications == * Khaled Rahmouni, Frédéric Pétrot[[BR]] ''Improving the tests coverage of a medium voltage protection device using system simulation approaches''.[[BR]] In Proceedings of the IEEE Symposium on Industrial Embedded Systems, pages 184-187, Trento, Italy, july 2010. * Khaled Rahmouni, Patrice Gerin, Sébastien Chabanet, Frédéric Pétrot and Paul Pianu.[[BR]] ''Modelling and Architecture Exploration of a Medium Voltage Protection Device''.[[BR]] In Proceedings of the IEEE Symposium on Industrial Embedded Systems, pages 46–49, Lausanne, Suisse, july 2009. * Alain Greiner, Frédéric Pétrot, Mathieu Carrier, Mounir Benabdenbi, Roselyne Chotin-Avot, Raphaël Labayrade.[[BR]] ''MP-SoC Architecture for an Obstacle Detection Application in Pre-Crash Situation''.[[BR]] Reconfigurable Communication Centric SoCs, July 2006, pp. 24–30. * Alain Greiner, Frédéric Pétrot, Mathie Carrier, Mounir Benabdenbi, Roselyne Chotin-Avot, Raphaël Labayrade.[[BR]] ''Mapping an obstacles detection, stereo vision-based, software application on a multi-processor System-on-Chip''.[[BR]] In IEEE Intelligent Vehicles Symposium, Tokyo, Japan, June 2006, pp. 370–376.