[[PageOutline]] = About SoCLib design = == TLM-DT == * Aline Vieira-de-Mello, Isaac Maia, Alain Greiner, François Pêcheux[[BR]] ''Parallel Simulation of SystemC TLM 2.0 Compliant MPSoC on SMP Workstations''[[BR]] At [http://www.date-conference.com/ Date'10] == ISS design == * Nicolas Pouillon, Alexandre Becoulet, Aline Vieira-de-Mello, François Pêcheux, Alain Greiner[[BR]] ''A Generic Instruction Set Simulator API for Timed and Untimed Simulation and Debug of MP2-!SoCs''[[BR]] At [http://www.rsp-symposium.org/ RSP'09], doi [http://dx.doi.org/10.1109/RSP.2009.11 10.1109/RSP.2009.11] [attachment:rsp_09_iss.pdf PDF] == Fast CABA simulation == * Richard Buchmann, Alain Greiner[[BR]] ''A Fully Static Scheduling Approach for Fast Cycle Accurate SystemC Simulation of MPSoCs''[[BR]] At [http://www.ieee-icm.com/2007/ ICM'07], doi: [http://dx.doi.org/10.1109/ICM.2007.4497671 10.1109/ICM.2007.4497671] = About studies evaluating modeling of hardware components = == NoC == * Alain Greiner, Sami Taktak, Zhen Zhang[[BR]] ''A Reconfigurable Routing Algorithm for a Fault-Tolerant 2D-Mesh Network-on-Chip''[[BR]] At [http://www2.dac.com/45th+dac+_2008_.aspx DAC'08], doi: [http://dx.doi.org/10.1145/1391469.1391584 10.1145/1391469.1391584] = Using SoCLib as virtual prototype = == MWMR == * Alain Greiner, Etienne Faure, Nicolas Pouillon, Daniela Genius[[BR]] ''A Generic Hardware / Software Communication Middleware for Streaming Applications on Shared Memory Multi Processor Systems-on-Chip''[[BR]] At [http://www.ecsi-association.org/ecsi/fdl/fdl09/mainpage.asp FDL'09], [http://www-asim.lip6.fr/pub/reports/2009/ar.grein.fdl.1.2009.pdf PDF] * Daniela Genius, Etienne Faure, Nicolas Pouillon[[BR]] ''Deploying a Telecommunication Application on Multiprocessor Systems-on-Chip''[[BR]] At [http://www.ecsi-association.org/ecsi/dasip/dasip07/main.asp?fn=def DASIP'07], [http://www-soc.lip6.fr/~genius/dasip.pdf PDF] == Packet networks == * Daniela Genius, Alix Munier Kordon, Khouloud Zine el Abidine[[BR]] ''A Buffer Space Optimal Solution for Re-establishing the Packet Order in a MPSoC Network Processor''[[BR]] At Europar'09 doi: [http://dx.doi.org/10.1007/978-3-642-03869-3_23 10.1007/978-3-642-03869-3_23]