| 1 | = GAUT = |
| 2 | |
| 3 | == General Presentation == |
| 4 | |
| 5 | GAUT is an academic High-Level Synthesis tool dedicated to Digital Signal Processing DSP applications. |
| 6 | |
| 7 | Starting from a pure C function GAUT extracts the potential parallelism before selecting/allocating operators, scheduling and binding operations. |
| 8 | |
| 9 | The mandatory design constraints are (1) the throughput (the initiation interval), (2) the clock period and (3) the target technology. The optional design constraints are I/O timing diagram and the memory mapping. |
| 10 | |
| 11 | GAUT synthesizes a potentially pipelined architecture composed of a processing unit, a memory unit, a communication and multiplexing unit and a GALS/LIS interface. |
| 12 | |
| 13 | GAUT generates an IEEE P1076 compliant RTL level VHDL file. This VHDL file is an input for commercial, off the shelf, logical synthesis tools like ISE/Foundation from Xilinx and Design Compiler from Synopsys. |
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| 16 | == More Information == |
| 17 | |
| 18 | You can obtain more detailed information, and download the tool [http://www-labsticc.univ-ubs.fr/www-gaut/ here] |