Changes between Initial Version and Version 1 of Vci Protocol


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Timestamp:
Mar 28, 2010, 12:17:31 PM (12 years ago)
Author:
Nicolas Pouillon
Comment:

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  • Vci Protocol

    v1 v1  
     1= VCI protocol adaptations for SoCLib =
     2
     3VCI has some ambiguous features, and other are unusable. Here we'll try to clarify the VCI extensions made in the SoCLib context.
     4
     5= Endianness =
     6
     7VCI is quite unclear about endianness interpretation. SoCLib defines some rules on top of VCI:
     8 * VCI addresses words. LSBs of addresses are non-significant. i.e. on a 32-data-bits VCI network, ADDR[1:0] are useless, and can be kept 0.
     9 * VCI subword addressing is done through BE field
     10  * BE![0] is associated to DATA![7:0]
     11  * BE![1] is associated to DATA![15:8]
     12  * BE![2] is associated to DATA![23:16]
     13  * BE![3] is associated to DATA![31:24]
     14 * DATA Words are little endian so considering an (aligned) address @ of a word in DATA,
     15  * byte at address @ is in DATA![7:0]
     16  * byte at address @+1 is in DATA![15:8]
     17  * byte at address @+2 is in DATA![23:16]
     18  * byte at address @+3 is in DATA![31:24]
     19
     20== Peripherals considerations ==
     21
     22It's up to the peripherals to define their endianness, i.e. the association between lower addresses and lower-significant-bits.
     23
     24As our convention aligns lower addressable byte to LSBs of DATA, thus is Little-Endian, it may be easier to have little-endian-only peripherals and use them seamlessly from any CPU with encapsulated accesses.
     25
     26== Memory considerations ==
     27
     28Memory is endianness-agnostic. It serves reading and writing from/to memory words (in the VCI way defined above)
     29
     30== Cache considerations ==
     31
     32VciXCache does not care about endianness of attached processor BUT asserts the VCI definitions above.
     33
     34When accessing memory with a big-endian processor, it's up to the processor to swap the word from LE to BE.
     35
     36= Atomic Operations =
     37
     38VCI defines a `LOCKED_READ` operation. Unfortunately, it can't be properly used with a NoC-based interconnect as putting the reservation on the "read" operation:
     39 * Can't guarantee the absence of livelocks
     40 * Necessitates the addition of a timeout mechanism to workaround software doing locked read without associated write.
     41
     42Therefore, SoCLib uses the "NOOP" VCI command code (redundant with CMDVAL = 0) to introduce the "Store conditional" mechanism.
     43
     44A "STORE_COND" response uses the RDATA field for STORE completion:
     45 `RDATA == 0`::
     46  STORE_COND was atomic
     47 `RDATA == 1`::
     48  STORE_COND was not atomic, a complete `LOCKED_READ` / `STORE_COND` cycle must be done again.