Changes between Version 40 and Version 41 of Wiki Start


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Timestamp:
Nov 5, 2008, 2:02:58 PM (17 years ago)
Author:
trac
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  • Wiki Start

    v40 v41  
    1 {{{
    2 #!html
    3 <h1 style="text-align: center; color: blue; font-size: 300%;">Welcome to SoCLib project home page</h1>
    41
    5 <div id="mainnav" class="nav"><ul><center>
    6   <li class="active first"><a accesskey="1" href="https://www.soclib.fr/trac/dev/wiki/Start">Enter technical part</a></li>
    7 <!-- <li><a accesskey="2" href="https://www.soclib.fr/trac/anr">Go to ANR page</a></li> -->
    8 </center></ul></div>
    9 }}}
    10 ----
     2Welcome to SoCLib's development Trac
    113
    12 = What is SoCLib =
     4[[PageOutline]]
    135
    14  * SoCLib is an open platform for virtual prototyping of multi-processors system on chip (MP-SoC).
    15  * The core of the platform is a library of SystemC simulation models for virtual components (IP cores), with a guaranteed path to silicon.
    16  * The project is funded by the french ''Agence Nationale pour la Recherche''.
    17  * 6 industrial companies and 11 laboratories are working together to build this platform
    18    * [http://www.magillem.com/ Magillem Design Services]
    19    * [http://www.silicomp.fr/ SILICOMP]
    20    * [http://www.st.com/stonline/fr/index.htm STMicrelectronics]
    21    * [http://www.thalesonline.com/ Thales Communications]
    22    * [http://www.thomson.net/GlobalEnglish/Pages/default.aspx Thomson R&D France]
    23    * [http://www.turboconcept.com/index.php TurboConcept]
    24    * [http://www-list.cea.fr/ CEA-LIST] Saclay
    25    * [http://www-leti.cea.fr/scripts/home/publigen/content/templates/show.asp?P=235&L=FR&MASTER=MASTER_WWWLETIHOME CEA-LETI] Grenoble
    26    * [http://www.citi.insa-lyon.fr/ CITI] Lyon
    27    * [http://www.enst.fr/ ENST] Paris
    28    * [http://www.inria.fr/saclay/ INRIA Futurs] Saclay
    29    * [http://www.irisa.fr/home_html IRISA] Rennes
    30    * [http://web.univ-ubs.fr/lester/www-lester/Index.php Lester] Lorient
    31    * [http://www.lip6.fr/fr/index.php LIP6] Paris
    32    * [http://www.lis.inpg.fr/ LIS] Grenoble
    33    * [http://www.lisif.jussieu.fr/ LISIF] Paris
    34    * [http://tima.imag.fr/ TIMA] Grenoble
     6= A) SoCLib Library =
    357
    36 = Technical features =
     8 * [wiki:Component SoCLib Components General Index] : contains documentation about the hardware components (IP cores) available in the SoCLib library.
    379
    38 The main concern is true interoperability between the SoCLib IP cores :
    39  * All simulation models are written in SystemC
    40  * All !SoCLib components respect the VCI /OCP communication protocol.
    41  * Two types of models are available for each IPcore : CABA (Cycle Accurate / Bit Accurate), and TLM-T (Transaction Level Modeling with Time)
     10= B) SoCLib OS & Middleware =
    4211
    43 = Availability =
     12 * [wiki:Tools/Muteka MutekA] : OS kernel for MPSoCs with support for POSIX threads
     13 * [wiki:Tools/Mutekh MutekH] : exo-kernel based OS kernel for MPSoCs with support for POSIX threads
     14 * [wiki:Tools/Muteks MutekS] : Optimised, static OS for DSX
     15 * [wiki:Tools/Mwmr MWMR] : Hardware / Software communication middleware
    4416
    45  * All simulation models and most associated tools are distributed as free software.
    46  * The !SoClib documentation can be accessed [https://www.soclib.fr/trac/dev/wiki/Start here]
    47  * To actually download one or several !SoClib tools or component, you must register below.
    48  * For each SoCLib component, a synthesizable RTL model is available, in order to guarantee a path to silicon, but this RTL model is  NOT part of the SoCLib library, in order to preserve the IP providers business.
     17= C) SoCLib Tools =
    4918
    50 ----
     19 * [wiki:Tools/Dsx DSX] : Design Space Exploration tool
     20 * [wiki:Tools/SystemCass SystemCASS] : Fast SystemC simulation kernel
     21 * [wiki:Tools/SocView SoCView] : Interactive simulation environment for debug and instrumentation
     22 * [wiki:Tools/GdbServer GdbServer] : A GDB server for multi-processor architectures
     23 * [wiki:Tools/VCI_Validation VCI Validation] : A library for the validation of the VCI protocol (CABA and TLM-T versions)
    5124
     25= D) SoCLib Resources =
    5226
    53 = Get your own copy =
     27== Mailing list ==
    5428
    55 If you haven’t already done it, please register to create your account !
     29The [mailto:dev@soclib.fr] Mailing list is public and targets general discussion about SoCLib component development.
    5630
    57 {{{
    58 #!html
    59 <form method="post" action="http://www.soclib.fr/cgi-bin/soclib_register">
    60   <table border="0" cellpadding="5" cellspacing="0">
    61     <tr>
    62       <td align="right" valign="center"><font face="Verdana, Arial, Helvetica, sans-serif" size="2">E-mail:</font></td>
    63   <td>
    64     <input type="text" name="email" size="45" maxlength="255">
    65   </td>
    66 <td height="32">&nbsp;</td>
    67 <td height="32"> <input type=submit name="register" value="Submit request"></td>
    68 </tr>
    69 </table>
    70 </form>
    71 }}}
     31To join the list, either
     32 * send an email to [mailto:dev-subscribe@soclib.fr];
     33 * see [http://www.soclib.fr/wws/info/dev].
    7234
    73 Please note that this e-mail will be your login ID!
     35==  Installation, usage ==
    7436
    75 You may also want to sign-up for the developers mailing list dev@soclib.fr, to do so please visit this [http://www.soclib.fr/wws/info/dev link].
     37 * [wiki:InstallationNotes Installation Notes] : how to install the SoCLib platform on your computer
     38 * SoclibCc is the current build system for SoCLib platforms
     39 * [wiki:AddComponent Adding new components to the library] : the rules to follow to add a new IP core to the library.
    7640
     41==  Writing and design guides ==
    7742
    78 If you need write access or for any other problem please [mailto:wahid.bahroun@lip6.fr?subject=SoCLib%20Request contact].
     43 * [wiki:WritingRules/General General SoCLib Rules] : general rules regarding the SoCLib components.
     44 * [wiki:WritingRules/Caba CABA Writing Rules] : rules to write SystemC CABA simulation models.
     45 * [wiki:WritingRules/Tlmt TLM-T Writing Rules] : rules to write SystemC TLM-T simulation models.
     46 * [wiki:WritingRules/RISC Processor Modeling] : a general method to write generic processor models.
     47 * [wiki:VciAndEndianness Endianness considerations] : Endianness rules in SoCLib
    7948
    80 ----
     49== Miscelaneous ==
    8150
     51 * [wiki:WritingRules/TLMT Critères Pour Plate-Forme TLM-T] : criteria defined for writing TLM-T simulation models.
     52 * [wiki:SoclibCc/DesignGuide SoclibCc/DesignGuide] is an attempt to justify the choices made in soclib-cc
     53 * [wiki:Models Models of documents] to be used by the project partners
     54 * [wiki:FrequentlyAskedQuestions Frequently asked questions]: When things goes wrong
     55
     56= E) Tutorials =
     57
     58 * [https://www-asim.lip6.fr/trac/dsx/wiki/MjpegCourse DSX tutorial]
     59 * [wiki:Motion-JPEG and OS tutorial]