{{{
#!html
<h1 style="text-align: center; color: blue">Welcome to SoCLib project home page</h1>
}}}

----

= Goals =

 * Build an open platform for modeling and simulation of multi-processors system on chip, that can be used by both universities and industrial companies.
 * The core of the platform is a library of simulation models for virtual components (IP cores), with a guaranteed path to silicon.
 * Create the largest possible cooperation project at European level, in order to share the development costs.

= Technical features =

The main concern is true interoperability between the SoCLib IP cores :
 * All simulation models written in SystemC
 * Two well defined abstraction levels have been defined :
   * CABA (Cycle Accurate / Bit Accurate)
   * TLM-T (Transaction Level Modeling with Time)
 * All SoCLib components respect the VCI communication protocol.

= Principles =

=== Openness ===

All simulation models are distributed as open source and available to all academic institutions and industrial company

=== Path to silicon ===

A synthesizable RTL model must exist for each SoCLib component, in order to guarantee a path to silicon for any system designed with the SoCLib library.

=== Business model ===

The RTL synthesizable models are NOT part of the SoCLib library, in order to preserve the IP providers business.

=== European scale ===

The SoCLib project was launched and is supported by the French CNRS (Centre National de la Recherche Scientifique), but is now part of the EUROSOC network.

= Partners =

6 industrial companies and 11 academic laboratories are contributing to the French SoCLib project :

 * [http://www.magillem.com/ Magillem Design Services]
 * [http://www.silicomp.fr/ SILICOMP]
 * [http://www.st.com/stonline/fr/index.htm STMicrelectronics]
 * [http://www.thalesonline.com/ Thales Communications]
 * [http://www.thomson.net/GlobalEnglish/Pages/default.aspx Thomson R&D France]
 * [http://www.turboconcept.com/index.php TurboConcept]

 * [http://www-list.cea.fr/ CEA-LIST] Saclay
 * [http://www-leti.cea.fr/scripts/home/publigen/content/templates/show.asp?P=235&L=FR&MASTER=MASTER_WWWLETIHOME CEA-LETI] Grenoble
 * [http://www.citi.insa-lyon.fr/ CITI] Lyon
 * [http://www.enst.fr/ ENST] Paris
 * [http://www.inria.fr/saclay/ INRIA Futurs] Saclay
 * [http://www.irisa.fr/home_html IRISA] Rennes
 * [http://web.univ-ubs.fr/lester/www-lester/Index.php Lester] Lorient
 * [http://www.lip6.fr/fr/index.php LIP6] Paris
 * [http://www.lis.inpg.fr/ LIS] Grenoble
 * [http://www.lisif.jussieu.fr/ LISIF] Paris
 * [http://tima.imag.fr/ TIMA] Grenoble


----


= Get your own copy =

First, you have to create an account, so, if you haven’t already done it, please register!

{{{
#!html
<form method="post" action="http://www.soclib.fr/cgi-bin/soclib_register">
  <table border="0" cellpadding="5" cellspacing="0">
    <tr>
      <td align="right" valign="center"><font face="Verdana, Arial, Helvetica, sans-serif" size="2">E-mail:</font></td>
  <td>
    <input type="text" name="email" size="45" maxlength="255">
  </td>
<td height="32">&nbsp;</td>
<td height="32"> <input type=submit name="register" value="Submit request"></td>
</tr>
</table>
</form>
}}}

Please note that this e-mail will be your login ID!

You may also want to sign-up for the developers mailing list dev@soclib.fr, to do so please visit this [http://www.soclib.fr/wws/info/dev link].


If you need write access or for any other problem please [mailto:wahid.bahroun@lip6.fr?subject=SoCLib%20Request contact me].


----

Then you’ll have to setup your environment and install the needed tools.

You’ll find all the necessary informations on the [https://www.soclib.fr/trac/dev/wiki/Start SoCLib development trac page].