= Technical features =

The main concern is true interoperability between the SoCLib IP cores :
 * All simulation models are written in SystemC
 * All !SoCLib components respect the VCI /OCP communication protocol.
 * Two types of models are available for each IPcore : CABA (Cycle Accurate / Bit Accurate), and TLM-T (Transaction Level Modeling with Time)

= Availability =

 * All simulation models and most associated tools are distributed as free software.
 * The !SoClib documentation can be accessed [https://www.soclib.fr/trac/dev/wiki/Start here]
 * To actually download one or several !SoClib tools or component, you must register below.
 * For each SoCLib component, a synthesizable RTL model is available, in order to guarantee a path to silicon, but this RTL model is  NOT part of the SoCLib library, in order to preserve the IP providers business.

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= Get your own copy =

If you haven’t already done it, please register to create your account !

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      <td align="right" valign="center"><font face="Verdana, Arial, Helvetica, sans-serif" size="2">E-mail:</font></td>
  <td>
    <input type="text" name="email" size="45" maxlength="255">
  </td>
<td height="32">&nbsp;</td>
<td height="32"> <input type=submit name="register" value="Submit request"></td>
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Please note that this e-mail will be your login ID!

You may also want to sign-up for the developers mailing list dev@soclib.fr, to do so please visit this [http://www.soclib.fr/wws/info/dev link].


If you need write access or for any other problem please [mailto:wahid.bahroun@lip6.fr?subject=SoCLib%20Request contact].

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