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= What is SocLib =

 * SoCLib is an open platform for virtual prototyping of multi-processors system on chip (MP-SoC).
 * The core of the platform is a library of SystemC simulation models for virtual components (IP cores), with a guaranteed path to silicon.
 * The project is funded by the french ''Agence Nationale pour la Recherche''.
 * 6 industrial companies and 11 laboratories are working together to build this platform
   * [http://www.magillem.com/ Magillem Design Services]
   * [http://www.silicomp.fr/ SILICOMP]
   * [http://www.st.com/stonline/fr/index.htm STMicrelectronics]
   * [http://www.thalesonline.com/ Thales Communications]
   * [http://www.thomson.net/GlobalEnglish/Pages/default.aspx Thomson R&D France]
   * [http://www.turboconcept.com/index.php TurboConcept]
   * [http://www-list.cea.fr/ CEA-LIST] Saclay
   * [http://www-leti.cea.fr/scripts/home/publigen/content/templates/show.asp?P=235&L=FR&MASTER=MASTER_WWWLETIHOME CEA-LETI] Grenoble
   * [http://www.citi.insa-lyon.fr/ CITI] Lyon
   * [http://www.enst.fr/ ENST] Paris
   * [http://www.inria.fr/saclay/ INRIA Futurs] Saclay
   * [http://www.irisa.fr/home_html IRISA] Rennes
   * [http://web.univ-ubs.fr/lester/www-lester/Index.php Lester] Lorient
   * [http://www.lip6.fr/fr/index.php LIP6] Paris
   * [http://www.lis.inpg.fr/ LIS] Grenoble
   * [http://www.lisif.jussieu.fr/ LISIF] Paris
   * [http://tima.imag.fr/ TIMA] Grenoble

= Technical features =

The main concern is true interoperability between the SoCLib IP cores :
 * All simulation models are written in SystemC
 * All !SoCLib components respect the VCI /OCP communication protocol.
 * Two types of models are available for each IPcore : CABA (Cycle Accurate / Bit Accurate), and TLM-T (Transaction Level Modeling with Time)

= Availability =

 * All simulation models and most associated tools are distributed as free software.
 * The !SoClib documentation can be accessed [https://www.soclib.fr/trac/dev/wiki/Start here]
 * To actually download one or several !SoClib tools or component, you must register below.
 * For each SoCLib component, a synthesizable RTL model is available, in order to guarantee a path to silicon, but this RTL model is  NOT part of the SoCLib library, in order to preserve the IP providers business.

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= Get your own copy =

If you haven’t already done it, please register to create your account !

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Please note that this e-mail will be your login ID!

You may also want to sign-up for the developers mailing list dev@soclib.fr, to do so please visit this [http://www.soclib.fr/wws/info/dev link].


If you need write access or for any other problem please [mailto:wahid.bahroun@lip6.fr?subject=SoCLib%20Request contact].

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