[[PageOutline]]

= What is SoCLib =

 * SoCLib is an open platform for virtual prototyping of multi-processors system on chip (MP-SoC).
 * The core of the platform is a library of SystemC simulation models for virtual components (IP cores), with a guaranteed path to silicon.
 * The project is funded by the french [http://www.agence-nationale-recherche.fr/ ''Agence Nationale pour la Recherche''].
 * It involves [wiki:SoCLibPartners 6 industrial companies and 11 laboratories] which are working together to build this platform

You may want to have a look at FeaturesDescription, or [GetAccount get an account]

= SoCLib Library =

== Code ==

 * [wiki:Component SoCLib Components General Index] : contains documentation about the hardware components (IP cores) available in the SoCLib library.

==  Installation, usage ==

 * [wiki:InstallationNotes Installation Notes] : how to install the SoCLib platform on your computer

== Development ==

 * [wiki:AddComponent Adding new components to the library] : the rules to follow to add a new IP core to the library.
 * SoclibCc is the current build system for SoCLib platforms

= SoCLib OS & Middleware =

 * [wiki:Tools/Muteka MutekA] : OS kernel for MPSoCs with support for POSIX threads
 * [wiki:Tools/Mutekh MutekH] : exo-kernel based OS kernel for MPSoCs with support for POSIX threads
 * [wiki:Tools/Muteks MutekS] : Optimised, static OS for DSX
 * [wiki:Tools/Mwmr MWMR] : Hardware / Software communication middleware

= SoCLib Tools =

 * [wiki:Tools/Dsx DSX] : Design Space Exploration tool
 * [wiki:Tools/SystemCass SystemCASS] : Fast SystemC simulation kernel
 * [wiki:Tools/SocView SoCView] : Interactive simulation environment for debug and instrumentation
 * [wiki:Tools/GdbServer GdbServer] : A GDB server for multi-processor architectures
 * [wiki:Tools/MemoryChecker MemoryChecker] : A memory access error checker similar to valgrind.
 * [wiki:Tools/VCI_Validation VCI Validation] : A library for the validation of the VCI protocol (CABA and TLM-T versions)
 * [wiki:Tools/GAUT GAUT] : A high-level synthesis tool allowing to generate automatically systemC CABA and TLM-T files.

= SoCLib Resources =

== Mailing list ==

The [mailto:dev@soclib.fr] Mailing list is public and targets general discussion about SoCLib component development.

To join the list, either
 * send an email to [mailto:dev-subscribe@soclib.fr];
 * see [http://www.soclib.fr/wws/info/dev].

==  Writing and design guides ==

 * [wiki:WritingRules/General General SoCLib Rules] : general rules regarding the SoCLib components.
 * [wiki:WritingRules/Caba CABA Writing Rules] : rules to write SystemC CABA simulation models.
 * [wiki:WritingRules/Tlmt TLM-T Writing Rules] : rules to write SystemC TLM-T simulation models.
 * [wiki:WritingRules/RISC Processor Modeling] : a general method to write generic processor models.
 * [wiki:VciAndEndianness Endianness considerations] : Endianness rules in SoCLib

== Miscelaneous ==

 * [wiki:WritingRules/TLMT Critères Pour Plate-Forme TLM-T] : criteria defined for writing TLM-T simulation models.
 * [wiki:SoclibCc/DesignGuide SoclibCc/DesignGuide] is an attempt to justify the choices made in soclib-cc
 * [wiki:Models Models of documents] to be used by the project partners 
 * [wiki:FrequentlyAskedQuestions Frequently asked questions]: When things goes wrong

= Tutorials =

 * [https://www-asim.lip6.fr/trac/dsx/wiki/MjpegCourse DSX tutorial]
 * [wiki:Motion-JPEG and OS tutorial]

= Posters and publications =

 * [attachment:PosterICT-Soclib-V5-HD.pdf]