Changes between Version 17 and Version 18 of Writing Rules/Caba
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- Apr 26, 2007, 4:15:01 PM (17 years ago)
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Writing Rules/Caba
v17 v18 4 4 }}} 5 5 [[PageOutline]] 6 = Introduction =6 = A) Introduction = 7 7 8 8 This manual describes the modeling rules for writing "cycle-accurate / bit-accurate" SystemC simulation models for SoCLib. Models complying with those rules can be used with the "standard" OSCI simulation engine (SystemC 2.x), but can be used also with others simulation engines, such as [SystemCass SystemCASS], which is optimized for such models. … … 23 23 In this figure we represented a single FSM, but a SoCLib component contains generally several small FSMs running in parallel inside a single module. This internal parallelism should be properly described. 24 24 25 = Components = 25 = B) CABA rules = 26 27 == B1) Components == 26 28 27 29 A SoCLib CABA simulation model for an hardware component `XXX` is generally described as a class derived from the 28 30 [source:trunk/soclib/systemc/include/caba/util/base_module.h soclib::caba::BaseModule] class. 29 30 31 31 32 32 At least two files are associated to each hardware component: … … 34 34 * `XXX.cc` contains the code of the methods associated to this component. 35 35 36 = VCI Interface=36 == B2) VCI Interface == 37 37 38 38 In order to enforce interoperability, all hardware architectures build with the SoCLib component library … … 73 73 A SoCLib hardware component that has no VCI interface should use a dedicated VCI wrapper in order to be connected to the VCI interconnect. 74 74 75 = Address space segmentation=75 == B3) Address space segmentation == 76 76 77 77 [[Image(WritingRules:guideline.png, nolink)]] … … 107 107 Any hardware component using the memory map should have a constant reference to the mapping table as constructor argument. 108 108 109 = Component ressources=109 == B4) Component definition == 110 110 111 111 [[Image(WritingRules:guideline.png, nolink)]] … … 113 113 The component ''XXX.h'' file contains the following informations 114 114 115 == Interface definition==115 === Interface definition === 116 116 117 117 A typical VCI target component will contain the following ports: … … 122 122 }}} 123 123 124 == Internal registers==125 126 All internal registers must be defined with the type ''sc_signal''124 === Internal registers definition === 125 126 All internal registers should be defined with the ''sc_signal'' type. 127 127 128 128 This point is a bit tricky: It allows the model designer to benefit from the delayed update … … 132 132 `sc_signal` type is considered as a register. 133 133 134 In order to improve the code readability, all internal registers should be prefixed with `r_`.135 136 134 A typical VCI target will contain the following registers : 137 135 {{{ … … 144 142 ''`typename vci_param::trdid_t` and others are generically-defined VCI field types'' 145 143 146 == Structural parameters==144 === Structural parameters definition === 147 145 148 146 All structural parameters must be be defined as member variables. The values are generally defined by a constructor argument. 149 147 Instance name is stored in [source:trunk/soclib/systemc/include/common/base_module.h soclib::common::BaseModule], inherited by 150 148 [source:trunk/soclib/systemc/include/caba/util/base_module.h soclib::caba::BaseModule]. 151 152 For a VCI target, assigned segment should be copied in order to check commands.149 For example, a VCI target will contain a reference to the the assigned segment, in order to check 150 possible segmentation errors during execution. 153 151 154 152 {{{ … … 156 154 }}} 157 155 158 = Constructor & destructor=156 == B5) Constructor & destructor == 159 157 160 158 Any hardware component must have an instance name, and most SoCLib component must have 161 a VCI index. Moreover, generic simulation models can have structural parameters defined as 162 arguments in the constructor, and used by the constructor to configure the hardware ressources. 163 A constructor argument frequently 164 used is a reference on the [source:trunk/soclib/systemc/include/common/mapping_table.h soclib::common::MappingTable], 165 that defines the segmentation of the system address space. 159 a VCI index. Moreover, generic simulation models can have structural parameters. The parameter 160 values must be defined as constructor arguments, and used by the constructor to configure the hardware ressources. A constructor argument frequently 161 used is a reference on the [source:trunk/soclib/systemc/include/common/mapping_table.h soclib::common::MappingTable], that defines the segmentation of the system address space. 166 162 A typical VCI component will have the following constructor arguments: 167 163 … … 174 170 175 171 In this example, the first argument is the instance name, the second argument is the VCI target index, and the third argument is the mapping table. 172 173 [[Image(WritingRules:mandatory.png, nolink)]] 176 174 177 175 Moreover, the constructor must define the sensitivity list of the Transition(), genMoore() and genMealy() … … 184 182 The register initialization must be an hardware mechanism explicitly described in the Transition function on reset condition. 185 183 186 = member functions = 187 188 The component behaviour is described by simple member functions. 189 190 == transition() method == 184 == B6) member functions == 185 186 The component behaviour is described by simple member functions. The type ot those methods 187 (Transition, genMoore, or genMealy) is defined by the sensitivity lists, as specified in B5. 188 189 === transition() method === 191 190 192 191 For each hardware component, there is only one `Transition()` method. It is called 193 192 once per cycle, as the sensitivity list contains only the clock rising edge. This method 194 193 computes the next values of the registers (variables that have the `sc_signal` type). 195 196 194 No output port can be assigned in this method. Each register should be assigned only once. 197 195 198 == genMoore() method==196 === genMoore() method === 199 197 200 198 For each hardware component, there is only one `genMoore()` method. It is called once 201 199 per cycle, as the sensitivity list contains only the clock falling edge. This method computes 202 200 the values of the Moore output ports. (variables that have the `sc_out` type). 203 204 201 No register can be assigned in this method. Each output port can be assigned only once. 205 202 No input port can be read in this method … … 207 204 == genMealy() method == 208 205 209 For each hardware component, there is zero, one or several `genMealy()` methods (one method 210 for each output port). These methods can be called several times per cycle. The sensitivity 211 list can contain several input ports. This method computes the Mealy values of the ouput ports, 212 using only the register values and the input ports values. 213 206 For each hardware component, there is zero, one or several `genMealy()` methods (it can be useful 207 to have one separated `gemealy()` method for each output port). These methods can be called several times per cycle. The sensitivity list can contain several input ports. This method computes the Mealy values of the ouput ports, using only the register values and the input ports values. 214 208 No register can be assigned in this method. Each output port can be assigned only once. 215 This method can use automatic variables. It can be missing if there is no Mealy output. 216 217 = Complete example = 209 210 = C) Complete example = 218 211 219 212 == C1) Component definition ==
