Changes between Version 9 and Version 10 of Writing Rules/RISC


Ignore:
Timestamp:
Jan 7, 2008, 7:58:12 PM (17 years ago)
Author:
alain
Comment:

--

Legend:

Unmodified
Added
Removed
Modified

  • Writing Rules/RISC

    v9 v10  
    1414
    1515The method relies on three basic principles :
    16 • The processor core is modeled as a generic ISS (Instruction Set Simulator).
    17 • This ISS is wrapped in apropriate wrappers for several types of simulation models : CABA, TLM-T and PV.
    18 • All processors types use the same generic cache controler.
     16 * The processor core is modeled as a generic ISS (Instruction Set Simulator).
     17 * This ISS is wrapped in apropriate wrappers for several types of simulation models : CABA, TLM-T and PV.
     18 * All processors types use the same generic cache controler.
    1919
    2020On one hand, the same ISS is encapsulated in different wrappers to generate several simulation models, corresponding to several abstraction levels: CABA (Cycle-Accurate Bit-Accurate), TLM-T (Transaction Level Models with Time), and PV (Programmer View, untimed). On the other hand, it is possible to use the same wrapper for different types of processor architectures. As illustrated below, all simulation models can be obtained as the cartesian product of the ISS set, by the wrappers set.
    … …  
    134134The CABA modeling for a complete CPU (processor + cache) is presented in figure 2.
    135135The processor ISS is wrapped in the generic CABA wrapper, implemented by the class '''!IssWrapper'''..
    136 The class '''!IssWrapper''' contains the member variable '''m_iss''' representing the processor ISS. The type of the '''m_iss''' variable - defining the type of the processor - is specified by the template parameter '''iss_t'''.
     136The class '''!IssWrapper''' contains the member variable '''m_iss''' representing the processor ISS. The type of the '''m_iss''' variable - defining the type of the processor - is specified by the template parameter '''iss_t'''. The class '''!VciXcache''' inherit the class '''caba::!ModuleBase''', that is the basis for all CABA modules.
    137137
    138138[[Image(caba_wrapper.png, nolink)]]
    139139
    140 To communicate with the '''!VciXcache''', the '''!IssWrapper''' class contains two member variables '''p_icache''', of type '''!IcacheProcessorPort''' and '''p_dcache''', of type '''!DcacheProcessorPort'''. It contains also the member variable '''p_irq''', That is a pointer to an array of ports of type '''sc_in<bool> *'''. This array represents the interrupt ports. The number N of interrupt ports depends on the wrapped processor, an is defined by the '''n_irq''' member variable of the '''iss_t''' class.
     140To communicate with the '''!VciXcache''', the '''!IssWrapper''' class contains two member variables '''p_icache''', of type '''!IcacheProcessorPort''' and '''p_dcache''', of type '''!DcacheProcessorPort'''. It contains also the member variable '''p_irq''', that is a pointer to an array of ports of type '''sc_in<bool>'''. This array represents the interrupt ports. The number N of interrupt ports depends on the wrapped processor, an is defined by the '''n_irq''' member variable of the '''iss_t''' class.
    141141
    142142The SystemC code for the generic CABA wrapper is presented below :
    … …  
    236236= F) TLM-T modeling =
    237237The TLM-T modeling for a complete CPU (processor + cache) is presented in figure 3.
    238 To increase the simulation speed, the TLM-T wrapper is the cache controler itself, and it is implemented as the class ''' !VciXcache'''. This class contains the SC_THREAD '''execLoop()''' implementing the PDES process, and the '''m_time''' member variable implementing the associated local clock. The class '''!VciXcache''' inherit the class '''Tlmt::!ModuleBase''', that is the basis for all TLM-T modules.
     238To increase the simulation speed, the TLM-T wrapper is the cache controller itself, and it is implemented as the class ''' !VciXcache'''. This class contains the SC_THREAD '''execLoop()''' implementing the PDES process, and the '''m_time''' member variable implementing the associated local clock. The class '''!VciXcache''' inherit the class '''tlmt::!ModuleBase''', that is the basis for all TLM-T modules.
    239239This class contains the member variable '''m_iss''' representing the processor ISS. The type of the '''m_iss''' variable is defined by the template parameter '''iss_t'''.
    240240
    … …  
    242242
    243243The class '''!VciXcache''' contain a member variable '''p_vci''', of type '''!VciInitPort''', to send VCI command packets, and receive VCI response packets.
    244 This class contains also N member variables '''p_irq[i]''', of type '''!SynchroInPort''', representing the interrupt ports. The number N of interrupt ports depends on the wrapped ISS, an is defined by the ‘’’n_irq’’’ member variable of the '''iss_t''' class.
     244This class contains also the member variable '''p_irq''', that is a pointer to an array of ports of type '''SynchroInPort'''. This array represents the interrupt ports. The number N of interrupt ports depends on the wrapped processor, an is defined by the '''n_irq''' member variable of the '''iss_t''' class.
    245245
    246246The '''execLoop()''' function contains an infinite loop. One iteration in this loop corresponds to one cycle for the local clock, (or more, as the thread is suspended in case of MISS).
    … …  
    253253}}}
    254254
    255 The ‘’’icache_request_t’’’, ‘’’dcache_request_t’’’, and ‘’’xcache_response_t’’’ classes represent the instruction and data requests, and the cache response respectively :
     255The '''icache_request_t''', '''dcache_request_t''', and '''xcache_response_t''' classes represent the instruction and data requests, and the cache response respectively :
    256256{{{
    257257class icache_request_t {
    … …  
    300300          uint32_t  icache_nlines,
    301301          uint32_t  icache_nwords)
    302     p_vci(« vci », this, &VciXcache::rspReceived, &m_time) ,
    303302    BaseModule(name),
    304303    m_iss(processorIdent),
    305304    m_time(0)
    306305    {
     306    p_vci(« vci », this, &VciXcache::rspReceived, &m_time) ,
    307307    for (uint32_t i = 0 ; i < iss_t::n_irq ; i++) {
    308308        new(&p_irq[i])SynchroInPort ("irq", i, this, &VciXcache::irqReceived) ;
    … …  
    329329uint32_t         m_lookahead ;
    330330uint32_t  m_counter ;
    331 bool  m_irqpending[iss_t ;;n_irq];
    332 uint32_t        m_irqtime[iss_t ::n_irq] ;
     331bool  m_irqpending[iss_t;;n_irq];
     332uint32_t        m_irqtime[iss_t::n_irq] ;
    333333vci_cmd_t m_cmd ;
    334334////////////////// thread
    … …  
    377377                xcache_response_t rsp)
    378378    {
     379    ...
    379380    } // end cacheAccess()
    380381
    … …  
    384385              uint32_t  time)
    385386    {
     387    ...
    386388    } // end rspReceived()
    387389